Tape circuit board and semiconductor chip package including...

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

Reexamination Certificate

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C174S263000, C257S779000

Reexamination Certificate

active

06737590

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-5868, filed on Feb. 7, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packaging technology and, more particularly, to a semiconductor chip package having a tape circuit board.
2. Description of the Related Arts
Recently, in order to meet the pressing demand for miniaturization, thinner profiles, higher integrity, higher speeds, and high pint counts in semiconductor packages, tape circuit boards have become increasingly popular. The tape circuit board includes an insulating thin base film made of a polyimide resin, wiring patterns on the base film, and connection leads connected to the wiring patterns. The tape circuit board employs a so-called “Tape Automated Bonding (TAB)” technique, where bumps on a semiconductor die are gang-bonded to the leads of the tape circuit board. Thus, the tape circuit board is referred to as a “TAB tape”. As one example of a semiconductor chip package using the tape circuit board, a Tape Carrier Package (TCP) is explained below.
FIG. 1
is a plan view of a conventional tape circuit board and
FIG. 2
is a cross-sectional view of a conventional tape carrier package.
Referring to FIG.
1
and
FIG. 2
, a conventional tape circuit board
110
includes an insulating base film
111
made of polyimide resin, an adhesive layer
112
formed on the base film
111
, and wiring patterns
115
formed on the adhesive layer
112
. The wiring patterns
115
are typically formed by laminating a Cu film and selectively photo-etching the Cu film. The wiring patterns
115
can be covered with a protection layer
116
made of solder resist, and leads
115
a
connected to the wiring patterns
115
are exposed from the protection layer
116
and extend across a window
113
.
Again referring to
FIG. 2
, a conventional carrier package
150
includes the tape circuit board
110
of
FIG. 1 and a
semiconductor chip
130
mounted on the tape circuit board
110
. The semiconductor chip
130
has chip bumps
135
and is flip-chip bonded to the tape circuit board
110
using the chip bumps
135
. The chip bumps
135
on electrode pads
131
of the semiconductor chip
130
are bonded to the leads
115
a
of the tape circuit board
110
. The electrical bonding portion between the semiconductor chip
130
and the tape circuit board
110
, the active and the side surfaces of the semiconductor chip
130
, and the exposed leads
115
a
are encapsulated with a potting resin, thereby forming a molding portion
140
.
Since this conventional tape carrier package uses a tape circuit board on which fine wiring patterns are formed, the distance and pitch between neighboring leads can be minimized, thus maximizing lead density. Further, this tape carrier package can employ semiconductor chips with a large number of chip pads and fine pitch or large-sized semiconductor chips. Therefore, the tape carrier package using the tape circuit board achieves high-integrated and multi-functional semiconductor device.
However, the conventional tape carrier package with the tape circuit board has several problems in meeting the demand for fine pitch of the chip pads of the semiconductor chip. That is, the tape carrier package is limited in its ability to decrease the pitch of the leads and to precisely align the chip bumps to the leads. Furthermore, the leads are exposed to the external environment before the molding step, which causes deformation or damage to the leads during the assembly process. Therefore, it is not easy to apply the tape circuit board to a tape carrier package with fine pitch, particularly 40 mm pitch.
In order to prevent the above-described problems, a Kapton-type transparent tape circuit board without a window for mounting semiconductor chips has been introduced. Similarly, as a package with fine pitch, a Chip On Film (COF) package is now being developed. The COF package has an excellent bending force and a good flexibility, compared to the conventional tape carrier package, is of high quality, thus meeting the demand of Active Matrix LCD devices (AMLCD). However, because this COF package has a two-layered structure, dissociation between the base film and a Cu layer occurs during High Temperature Storage (HTS) test, and since the film needs to be unloaded, mass production is difficult. Therefore, if a tape circuit board that could be applied to the fine pitch semiconductor chip package were developed, mass production can be accomplished.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a tape circuit board for application to a fine pitch semiconductor chip package, a method for manufacturing the tape circuit board, and a semiconductor chip package using the tape circuit board.
In order to achieve the foregoing and other objects, a tape circuit board includes an insulating base film having a first surface and a second surface. An adhesive layer is formed on the first surface of the base film. Further, wiring patterns are formed on the adhesive layer. Conductive bumps extend through the base film and the adhesive layer and are connected to the wiring patterns. The conductive bumps extend above the second surface of the base film.
Preferably, the bumps are disposed in plural columns, and bumps in one column are not aligned with the bumps in adjoining columns. A window for mounting a semiconductor chip is formed through the tape circuit board, and the bumps are formed on the tape circuit board around the window. The bumps are formed on two sides or four sides around the window.
According to another embodiment of the present invention, a method of manufacturing tape circuit boards is provided. According to one embodiment of the present invention, the method comprises: (a) preparing an insulating base film having a first and a second surface, the first surface on which an adhesive layer is formed; (b) forming bump holes penetrating the adhesive layer and the base film, and a window for mounting a chip; (c) forming wiring patterns on the adhesive layer; (d) coating the wiring patterns with a protection layer; (e) forming a photoresist layer on the second layer of the base film so that the bump holes are open; (f) forming bumps connected to the wiring patterns by filling the bump holes using the photoresist layer as a mask; and (g) removing the photoresist layer.
Preferably, in step (f), the bumps extend above the second surface of the base film. After step (g), the manufacturing method may comprise polishing the bumps or applying a cover film on the second surface of the base film.
In still another aspect of the present invention, a semiconductor chip package comprises: a tape circuit board including a base film having a first and a second surface, the first surface on which an adhesive layer is formed; wiring patterns formed on the first surface of the base film; and bumps passing through the base film and the adhesive layer, connected to the wiring patterns, and extending above the second surface of the base film; a semiconductor chip having a plurality of electrode pads and chip bumps formed on the electrode pads, wherein the chip bumps are bonded to the bumps of the tape circuit board; and a molding portion for molding a bonding portion between the tape circuit board and the semiconductor chip, and the active and the side surfaces of the semiconductor chip.
Preferably, the bumps of the tape circuit board and the chip bumps of the semiconductor chip are made of the same material and a protection layer covers the wiring patterns.


REFERENCES:
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patent: 5956606 (1999-09-01), Burnette
patent: 5986348 (1999-11-01), Fukano
patent: 6011694 (2000-01-01), Hirakawa
patent: 6046910 (2000-04-01), Ghaem et al.
patent: 6097610 (2000-08-01), Hashimoto
patent: 6114754 (2000-09-01), Kata
patent: 6150194 (2000-11-01), Sakaguchi et al.
patent: 6362436 (2002-03-01), Kimbara et al.
patent: 6509643 (2003-01-01),

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