Tap connections for circuits with leakage suppression...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reissue Patent

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C257S204000, C257S206000, C257S207000, C257S208000, C257S369000, C257S371000, C257SE21630, C257SE27107, C257SE27108, C257SE27067, C257S355000, C257S356000, C257S357000, C257S358000, C257S360000, C257S363000, C257S291000, C257S338000

Reissue Patent

active

RE042776

ABSTRACT:
An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

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patent: 5576570 (1996-11-01), Ohsawa et al.
patent: 5610550 (1997-03-01), Furutani
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patent: 6157070 (2000-12-01), Lin et al.
patent: 6376287 (2002-04-01), Dennison et al.
Robert F. Pierret, “Semiconductor Device Fundamentals with Computer-Based Exercises Homework Problems,” pp. 680-681.
Neil H. E. Weste Kamran Eshraghian, “Principles of CMOS VSLI Design, a Systems Perspective,” 2nd Ed., pp. 51, 54-55.

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