Tamper resistant packaging and approach

Details Tamper resistant packaging and approach Tamper resistant packaging and approach

2003-12-15

2009-02-03

Andújar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

With means to prevent inspection of or tampering with an...

C257S798000, C257S659000, C257S660000, C257SE23007, C257S701000, C257S702000, C257S724000, C257S736000, C257S782000, C713S194000, C340S539310

Reexamination Certificate

active

07485976

ABSTRACT:
A tamper-resistant packaging approach protects non-volatile memory. According to an example embodiment of the present invention, an array of magnetic memory elements (130-132) in an integrated circuit (100) are protected from magnetic flux(122) by a package (106) including a magnet (120). Flux from the magnet is directed away from the magnetic memory elements by the package. When tampered with, such as by removal of a portion of the package for accessing the magnetic memory elements, the package allows the flux to reach some or all of the magnetic memory elements, which causes a change in a logic state thereof. With this approach, the magnetic memory elements are protected from tampering.

REFERENCES:
patent: 6194888 (2001-02-01), Matsumoto et al.
patent: 6404674 (2002-06-01), Anthony et al.
patent: 2001/0005011 (2001-06-01), Minakata et al.
patent: 2001/0033012 (2001-10-01), Kommerling et al.
“Self-Destructing Diskette” IBM Technical Disclosure Bulletin (Jun. 1, 1990): 218-219.

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