Tamper detectable electronic security package

Details Tamper detectable electronic security package Tamper detectable electronic security package

1993-05-06

1996-04-09

Mullen, Thomas

Communications: electrical

Condition responsive indicating system

Specific condition

340658, G08B 1300

Patent

active

055065660

ABSTRACT:
An intrusion detection electronic circuit package, includes a containment wall in combination with first and second transmission lines being organized in patterns spaced adjacent one another. Electronic circuitry, residing within the containment wall, includes a transmitter for transmitting signals in anti-phase relationship via the first and second transmission lines respectively. A receiver receives signals from the transmission lines and a detector connected to the receiver uses EXCLUSIVE OR logic to detect any significant in-phase components or interruptions in the signals received at the first and second inputs of the receiver. Disturbance of either transmission line in any attempt to breach the containment wall is likely to be detected.

REFERENCES:
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patent: 4419659 (1983-12-01), Harman et al.
patent: 4538527 (1985-09-01), Kitchen
patent: 4777476 (1988-10-01), Dank
patent: 4884061 (1989-11-01), Genevois
patent: 5285734 (1994-02-01), MacPherson
Wiengart, S. H. "Physical Security for the uABYSS System", from Proceedings of the IEEE Symposium on Security and Privacy, Apr. 27-29, 1987, Oakland, California, pp. 52-58.
Chaum, D. "Design Concepts for Tamper Responding Systems", Advances in Cryptology, Proceedings of Crypto '83, Plenum Press 1984, pp. 387-392.

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