Tag design for cache access with redundant-form address

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S230030, C365S230040, C365S200000

Reexamination Certificate

active

06707752

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to field of memories particularly those using redundant-form addresses.
PRIOR ART AND RELATED ART
The latency of on-chip caching has become more and more important to the overall performance of microprocessors. To speed up cache access, a redundant-form addressing system is known which permits cache access before the final complete address becomes available. In general, the ordinary binary address is replaced with a more complex address (redundant-form). In effect, address components from an adder are used since these are more quickly available. For instance, these components are not delayed by the carry chain needed to complete the ordinary address. Aspects of this technology are described in PCT Application WO 99/64953; co-pending application Ser. No. 09/532,411 entitled “Shared Cache Word Line Decoder For Redundant And Regular Addresses” filed Mar. 22, 2000; and application Ser. No. 09/538,553 entitled “Cache Column Multiplexing Using Redundant Form Addresses” filed Mar. 29, 2000.
One problem associated with using redundant-form addresses is that it is costly to do redundant-form tag compares. Substantial additional circuitry is required to handle the redundant-form tag comparison.
As will be seen, the present invention solves this problem.


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