t.sub.RAS protection circuit

Details t.sub.RAS protection circuit t.sub.RAS protection circuit

1997-02-28

1997-12-30

Le, Vu A.

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 700

Patent

active

057038325

ABSTRACT:
Circuits and methods are disclosed to protect dynamic random access memory cell data from being destroyed when the minimum t.sub.RAS specification is not being adhered to, by holding off the already issued Row Precharge command until such time that t.sub.RAS is satisfied. The memory cell data is getting protected by providing a timing reference circuit with a delay .tau., where this delay tracks the bitline restore time of the memory array cell, a row activation control logic which holds off the row precharge cycle until time .tau. has elapsed, insuring that the bitline signals are fully restored, and an internal circuitry which provides a high isolation voltage for the bitline isolation devices and for a charging transistor in the timing reference circuit.

REFERENCES:
patent: 4998222 (1991-03-01), Sussman
patent: 5185719 (1993-02-01), Dhong et al.
patent: 5522064 (1996-05-01), Aldereguia et al.
patent: 5544115 (1996-08-01), Ikeda
patent: 5563831 (1996-10-01), Ting
patent: 5617362 (1997-04-01), Mori et al.

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