Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Bidirectional rectifier with control electrode
Reexamination Certificate
2001-04-16
2002-12-10
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Bidirectional rectifier with control electrode
C257S133000, C257S296000, C257S300000
Reexamination Certificate
active
06492662
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a Thyristor Random Access Memory (T-RAM) structure and method for fabricating the same. The T-RAM structure has dual vertical devices and a planar cell structure.
BACKGROUND OF THE INVENTION
A low-power, high-speed and high-density negative differential resistance (NDR) based (NDR-based) SRAM cell which can provide DRAM-like densities at SRAM-like speeds has been proposed by Farid Nemati and James D. Plummer in “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device,” 1998 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pages 66-67, 1998.
The memory device structure is shown by FIG.
1
and is designated by reference numeral
10
; the memory device structure is called a Thyristor-based Random Access Pi Memory (T-RAM) cell. The T-RAM device or memory cell
10
consists of a thin vertical pnpn thyristor
12
with a surrounding nMOS gate
14
as the bistable element and a planar nMOSFET as the access transistor
16
. The circuit schematic of the T-RAM cell
10
is shown by FIG.
2
.
To access the T-RAM cell
10
, two wordlines are necessary. The first wordline WL
1
is used to control an access gate of the transfer nMOSFET device
16
, while the second wordline WL
2
is the surrounding nMOS gate
14
which is used to control the switch of the vertical pnpn thyristor
12
. The thyristor
12
is connected to a reference voltage Vref. The second wordline WL
2
improves the switching speed of the thyristor
12
from 40 ns to 4 ns with a switching voltage. A bitline BL connects the T-RAM cell
10
to a sense amplifier for reading and writing data from and to the T-RAM cell
10
. The T-RAM cell
10
exhibits a very low standby current in the range of
10
pA.
When writing a “high”, the bitline BL is set at low, and both wordlines WL
1
, WL
2
are switched on. At this moment, the thyristor
12
behaves like a forward biased pn diode. After a write operation, both gates are shut off, and a “high” state is stored in the thyristor
12
. In a read operation, only the first wordline WL
1
is activated, a large “on” current will read on the bitline BL through the access gate. When writing a “low”, the bitline BL is set at “high” state, and both wordlines WL
1
, WL
2
are switched on. At this moment, the thyristor
12
behaves like a reverse biased diode. After the write operation, both gates are shut off, and a “low” state is stored in the thyristor
12
. Similarly, in a consequence read, a very low current will be detected on the bitline BL. Further details of the operation of the T-RAM cell
10
and its gate-assisted switching are described in Nemati et al.; the contents of which are incorporated herein by reference.
A T-RAM array having a plurality of T-RAM cells
10
has demonstrated a density equivalent to that of DRAM arrays and a speed equivalent to that of SRAM arrays. Hence, the T-RAM array provides advantages afforded by both SRAM and DRAM arrays. These advantages make T-RAM an attractive choice for future generations of high speed, low-voltage, and high-density memories and ASICs.
However, there are several drawbacks of the T-RAM cell
10
. First, there is the requirement of forming the thyristor
12
having a vertical pillar on a substrate during a fabrication process. Difficulties arise in controlling the dimensions of the vertical pillar and reproducing these dimensions for each T-RAM cell
10
in the T-RAM array. Second, due to the existence of a vertical thyristor
12
in each T-RAM cell
10
, each T-RAM cell
10
is not planar and therefore difficult to scale. Third, it is difficult to control the dimension while forming the surrounding gate around the base of each vertical thyristor
12
. Fourth, each T-RAM cell is fabricated prior to or after fabricating any other devices, such as P-MOS and n-MOS support devices (i.e., sense amplifiers, wordline drivers, column and row decoders, etc.), which results in extra fabrication steps, thereby increasing thermal budget and manufacturing cost. Finally, due to these drawbacks, the resulting T-RAM cell
10
cannot be smaller than 8F
2
and the cost of fabricating a T-RAM array is high.
SUMMARY
An aspect of the present invention is to provide a T-RAM array having a planar cell structure for overcoming the disadvantages of the prior art.
Another aspect of the present invention is to provide a T-RAM array having a plurality of T-RAM cells, wherein each of the plurality of T-RAM cells has a planar cell structure and dual vertical devices, i.e., a vertical thyristor and a vertical transfer gate.
Also, another aspect of the present invention is to provide a memory system having a plurality of T-RAM cells arranged in an array, wherein each of the plurality of T-RAM cells has a planar cell structure and dual vertical devices, i.e., a vertical thyristor and a vertical transfer gate.
Further, another aspect of the present invention is to provide a method for fabricating a high-density, high-yield and low-cost T-RAM array having a plurality of T-RAM cells and a planar cell structure on a SO
1
substrate. Each of the plurality of T-RAM cells has a planar cell structure and dual vertical devices, i.e., a vertical thyristor and a vertical transfer gate.
Finally, another aspect of the present invention is to provide a method for fabricating a T-RAM array which improves performance and yield, and reduces cost and thermal budget.
Accordingly, in an embodiment of the present invention, a T-RAM array is presented having a planar cell structure and a plurality of T-RAM cells where each T-RAM cell has dual vertical devices. That is, each T-RAM cell has a vertical thyristor and a vertical transfer gate. A top surface of each thyristor is coplanar with a top surface of each transfer gate within the T-RAM array to provider the planar cell structure for the T-RAM array. The inventive structure of each T-RAM cell results in higher performance at low voltage, e.g., Vdd=1V.
In another embodiment of the present invention, a memory system is presented having a plurality of T-RAM cells arranged in an array. Each of the T-RAM cells in the array has a planar cell structure and dual vertical devices, i.e., a vertical thyristor and a vertical transfer gate.
Further still, in another embodiment of the present invention, a method is presented for fabricating a T-RAM array having a planar cell structure. Each of the T-RAM cells in the T-RAM array has dual vertical devices, i.e., a vertical thyristor and a vertical transfer gate. The method entails forming the vertical devices in trenches of the same base, such that alignment of the transfer gate to a channel region in each T-RAM cell is highly reproducible. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SO
1
) wafer to reduce junction capacitance and improve scalability.
REFERENCES:
patent: 2001/0024841 (2001-09-01), Noble et al.
A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memoriesby Farid Nemati and James D. Plummer, Sep. 1999 IEEE, pp. 283-286.
A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Deviceby Farid Nemati and James D. Plummer, Jun. 1998 IEEE, pp. 66 and 67.
Hsu Louis L.
Joshi Rajiv V.
Dilworth & Barrese LLP
IBM Corporation
Wojciechowicz Edward
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