Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device
Reexamination Certificate
2005-06-14
2005-06-14
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
C257S121000, C257S124000
Reexamination Certificate
active
06906354
ABSTRACT:
A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath the horizontally stacked pseudo-TFT transfer gate. A method is also presented for fabricating the T-RAM array having the buried vertical thyristors, the horizontally stacked pseudo-TFT transfer gates and the planar cell structure.
REFERENCES:
patent: 89024 (1869-04-01), Carpenter
patent: 96689 (1869-11-01), Button
patent: 109150 (1870-11-01), Sterling
patent: 158254 (1874-12-01), Curzon
patent: 4060738 (1977-11-01), Tasch et al.
patent: 4554644 (1985-11-01), Chen et al.
patent: 5357125 (1994-10-01), Kumagi
patent: 5514882 (1996-05-01), Shulman
patent: 5543639 (1996-08-01), Nakanishi et al.
patent: 5659185 (1997-08-01), Iwamuro
patent: RE36770 (2000-07-01), Piccone
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6441406 (2002-08-01), Nakanishi et al.
patent: 6448586 (2002-09-01), Nemati et al.
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6465830 (2002-10-01), Babcock et al.
patent: 6465848 (2002-10-01), Ker et al.
patent: 6472686 (2002-10-01), Shah
patent: 6492662 (2002-12-01), Hsu et al.
patent: 4210071 (1993-09-01), None
patent: A 559133 (1992-03-01), None
patent: A 533439 (1993-03-01), None
A Novel-Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memoriesby Farid Nemati and James D. Plummer, Center for Integrated Systems, Stanford, University, 1999.
A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device, by Farid Nemati and James D. Plummer, Center for Integrated Systems, Stanford University, 1998.
Assaderaghi Fariborz
Hsu Louis L.
Joshi Rajiv V.
International Business Machines - Corporation
Percello Louis J.
Pham Long
Rao Shrinivas H.
LandOfFree
T-RAM cell having a buried vertical thyristor and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with T-RAM cell having a buried vertical thyristor and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and T-RAM cell having a buried vertical thyristor and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3477578