Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Heterojunction formed between semiconductor materials which...
Reexamination Certificate
2001-01-26
2004-03-30
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Heterojunction formed between semiconductor materials which...
C257S133000, C257S147000, C257S162000
Reexamination Certificate
active
06713791
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a Thyristor Random Access Memory (T-RAM) array having a planar cell structure and method for fabricating the same.
BACKGROUND OF THE INVENTION
A low-power, high-speed and high-density negative differential resistance (NDR) based (NDR-based) SRAM cell which can provide DRAM-like densities at SRAM-like speeds has been proposed by Farid Nemati and James D. Plummer in “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device,” 1998 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pages 66-67, 1998.
The memory device structure is shown by FIG.
1
and is designated by reference numeral
10
; the memory device structure is called a Thyristor-based Random Access Memory (T-RAM) cell. The T-RAM cell
10
consists of a thin vertical pnpn thyristor
12
with a surrounding nMOS gate
14
as the bistable element and a planar nMOSFET as the access transistor
16
. The circuit schematic of the T-RAM cell
10
is shown by FIG.
2
.
To access the T-RAM cell
10
, two wordlines are necessary. The first wordline WL
1
is used to control an access gate of the transfer nMOSFET device
16
, while the second wordline WL
2
is the surrounding nMOS gate
14
which is used to control the switch of the vertical pnpn thyristor
12
. The thyristor
12
is connected to a reference voltage Vref. The second wordline WL
2
improves the switching speed of the thyristor
12
from 40 ns to 4 ns with a switching voltage. A bitline BL connects the T-RAM cell
10
to a sense amplifier for reading and writing data from and to the T-RAM cell
10
. The T-RAM cell
10
exhibits a very low standby current in the range of 10 pA.
When writing a “high”, the bitline BL is set at low, and both wordlines WL
1
, WL
2
are switched on. At this moment, the thyristor
12
behaves like a forward biased pn diode. After a write operation, both gates are shut off, and a “high” state is stored in the thyristor
12
. In a read operation, only the first wordline WL
1
is activated, a large “on” current will read on the bitline BL through the access gate. When writing a “low”, the bitline BL is set at “high” state, and both wordlines WL
1
, WL
2
are switched on. At this moment, the thyristor
12
behaves like a reverse biased diode. After the write operation, both gates are shut off, and a “low” state is stored in the thyristor
12
. Similarly, in a consequence read, a very low current will be detected on the bitline BL. Further details of the operation of the T-RAM cell
10
and its gate-assisted switching are described in Nemati et al.; the contents of which are incorporated herein by reference.
A T-RAM array having a plurality of T-RAM cells
10
has demonstrated a density equivalent to that of DRAM arrays and a speed equivalent to that of SRAM arrays. Hence, the T-RAM array provides advantages afforded by both SRAM and DRAM arrays. These advantages make T-RAM an attractive choice for future generations of high speed, low-voltage, and high-density memories and ASICs.
However, there are several drawbacks of the T-RAM cell
10
. First, there is the requirement of forming the thyristor
12
having a vertical pillar on a substrate during a fabrication process. Difficulties arise in controlling the dimensions of the vertical pillar and reproducing these dimensions for each T-RAM cell
10
in the T-RAM array. Second, due to the existence of a vertical thyristor
12
in each T-RAM cell
10
, each T-RAM cell
10
is not planar and therefore difficult to scale. Third, it is difficult to control the dimension while forming the surrounding gate around the base of each vertical thyristor
12
. Fourth, each T-RAM cell is fabricated prior to or after fabricating any other devices, such as p-MOS and n-MOS support devices (i.e., sense amplifiers, wordline drivers, column and row decoders, etc.), which results in extra fabrication steps, thereby increasing thermal budget and manufacturing cost. Finally, due to these drawbacks, the resulting T-RAM cell
10
cannot be smaller than 8F
2
and the cost of fabricating a T-RAM array is high.
SUMMARY
An aspect of the present invention is to provide a T-RAM array having a planar cell structure for overcoming the disadvantages of the prior art.
Another aspect of the present invention is to provide a T-RAM array having a plurality of T-RAM cells, wherein each of the plurality of T-RAM cells has a planar cell structure and includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with the T-RAM cells. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.
Also, another aspect of the present invention is to provide a memory system having a plurality of T-RAM cells arranged in an array, wherein each of the plurality of T-RAM cells has a planar cell structure and includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with the T-RAM cells.
Further, another aspect of the present invention is to provide a method for fabricating a high-density, high-yield and low-cost T-RAM array having a planar cell structure on a SOI substrate.
Finally, another aspect of the present invention is to provide a method for fabricating a T-RAM array which improves the yield, reduces cost and thermal budget by sharing process implant steps among different devices, e.g., the plurality of T-RAM cells of a T-RAM array, the n-MOS and p-MOS support devices, etc., and allows for scaling based on the lithographic ground rule. The shared processes can be ion implantation, diffusion, annealing and silicidation.
Accordingly, in an embodiment of the present invention, a T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array.
In another embodiment of the present invention, a T-RAM array having a plurality of T-RAM cells is presented, wherein each of the T-RAM cells has a planar cell structure and the array includes n-MOS and p-MOS support devices. Process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS s.
Further, in another embodiment of the present invention, a memory system having a plurality of T-RAM cells arranged in an array. Each of the T-RAM cells in the array has a planar cell structure and the array includes n-MOS and p-MOS s interconnected with the plurality of T-RAM cells. Process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS s.
Further still, in another embodiment of the present invention, a method is presented for fabricating a T-RAM array having a planar cell structure. Each of the T-RAM cells in the T-RAM array is fabricated while fabricating n-MOS and p-MOS s. The method entails fabricating a first portion of a T-RAM cell, while fabricating the n-MOS (i.e., simultaneously fabricating the first portion of the T-RAM cell and the n-MOS support device); fabricating a second portion of the T-RAM cell, while fabricating the p-MOS support device (i.e., simultaneously fabricating the second portion of the T-RAM cell and the p-MOS support device); and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices.
In particular, a method is presented for fabricating a T-RAM array having a plurality of T-RAM cells and first and second devices on a semiconductor wafer. The method includes the steps of simultaneously fabricating a first portion of each of the plurality of T-RAM cells and the first devices; and simultaneously fabricating a second portion of each of the plurality of T-RAM cells and the second devices. The first portion of each of the plurality of T-RAM cells is a transfer gate and the second portion of each of the plurality of T-RAM cells is a gated-lateral thyristor storage element.
Accordingly, process steps in fabricating the T-RAM cells are
Assaderaghi Fariborz
Culp James
Hsu Louis L.
Joshi Rajiv V.
Moy Dan
Dilworth & Barrese LLP
IBM Corporation
Nguyen Dao H.
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