Systolic ring-planarized cylindrical array modular multipler

Details Systolic ring-planarized cylindrical array modular multipler Systolic ring-planarized cylindrical array modular multipler

2006-03-07

2006-03-07

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07010561

ABSTRACT:
A fast, scalable, systolic modular multiplier based on projection onto planar ring structures is presented. Systolic paradigms of limited fan-out on all signal paths and nearest neighbor interconnections guarantee optimally fast clock rates. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations.

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