Systolic linear-array modular multiplier with pipeline processin

Details Systolic linear-array modular multiplier with pipeline processin Systolic linear-array modular multiplier with pipeline processin

1997-10-10

2000-05-09

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

060617063

ABSTRACT:
A systolic linear-array modular multiplier is provided, which can perform the modular multiplication algorithm of P. L. Montgomery more efficiently. The total execution time for n-bit modular multiplication is 2n+11 cycles. The modular multiplier includes a linear array of processing elements which is constructed based on a pipeline architecture that can reduce the computation procedure by one clock period. Each of the processing elements is simple in structure, which is composed of four full adders and fourteen flip-flops. For n-bit modular multiplication, a total number of 46n+184 gates is required, which is substantially less as compared to the prior art, so that manufacturing cost of the modular multiplier can be significantly reduced. These features make the modular multiplier suitable for use in VLSI implementation of modular exponentiation which is the kernel computation in many public-key cryptosystems, such as the RSA (Rivest-Shamir-Adleman) system. With the 0.8 .mu.m CMOS technology, a clock signal up to 180 MHz can be used. In average, for n-bit modular multiplication, the encryption speed can reach 116 Kbit/s (kilobits per second), which is substantially twice that achieved by the prior art.

REFERENCES:
patent: 4797848 (1989-01-01), Walby
patent: 5101431 (1992-03-01), Even
patent: 5313530 (1994-05-01), Iwamura
patent: 5414651 (1995-05-01), Kessels

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