Systolic equalizer and method of using same

Details Systolic equalizer and method of using same Systolic equalizer and method of using same

2006-02-21

2006-02-21

Fan, Chieh M. (Department: 2638)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S229000

Reexamination Certificate

active

07003055

ABSTRACT:
A method and apparatus provide a systolic equalizer for Viterbi equalization of an 8-PSK signal distorted by passage through a communication channel. The systolic equalizer architecture is scalable to process, as examples, four, eight and 16 state received signals. An equalizer in accordance with this invention includes a logical arrangement of a plurality of instantiations of locally coupled processing elements forming a systolic array for processing in common received signal samples having distortion induced by passage through a communication channel. The equalizer outputs soft values for input to a decoder, the soft values representing an approximation of maximum a posteriori (MAP) probabilities. A trellis search procedure is employed to reconstruct estimates of a received signal sequence based on a reduced number of states. The reduced number of states is represented by a plurality of groups determined by partitioning a symbol constellation such that there are fewer groups than possible symbols.

REFERENCES:
patent: 5042036 (1991-08-01), Fettweis
patent: 2002/0181621 (2002-12-01), Bohnhoff et al.
patent: 2003/0053535 (2003-03-01), Malkov et al.
Lloyd, A.H., Reynolds, M.R., & Shah, Y.C.; “VLSI Architectures for Viterbi Decoding”; PA Consulting Group, Chapter 6, pp. 1-7.
Chakraborty, M., Pervin, S.; “A Systolic Array Realization of the Adaptive Decision Feedback Equalizer”; Signal Processing, pp. 2633-2640, (2000).
Fettweis, G., & Meyr, H.; “High-Rate Viterbi Processor: A Systolic Array Solution”; IEEE Journal, vol. 8, No. 8, pp. 1520-1534, Oct. 1990.
Hemkumar, N., Kota, K., & Cavallaro, J.; “Cape-VLSI Implementation of a Systolic Processor Array: Architecture, Design & Testing”; IEE Journal, Dept. of Electrical & Computer Engineering; pp. 64-69, (1991).
Koch, W . & Baier, A.; “Optimum and Sub-Optimum Detection of Coded Data Disturbed by Time-Varying Intersymbol Interference”; Philips Kommunikations Industrie AG, Germany; IEEE; pp. 1679-1684; (1990).
Gulak, P.G. & Kailath, T.; “Locally Connected VLSI Architectures for the Viterbi Algorithm”; IEEE Journal; vol. 6, No. 3, pp. 527-537, Apr. 1988.
Eyuboglu, M.V. & Qureshi, S.U.H.; “Reduced-State Sequence Estimation with Set Partitioning and Decision Feedback”; IEEE Journal; vol. 36, No. 1, pp. 13-20, Jan. 1988.

Affiliated with

Also associated with

Rating

Systolic equalizer and method of using same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systolic equalizer and method of using same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systolic equalizer and method of using same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3655804