Systolic cylindrical array modular multiplier

Details Systolic cylindrical array modular multiplier Systolic cylindrical array modular multiplier

2005-06-14

2005-06-14

Malzahn, D. H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06907440

ABSTRACT:
A fast, scalable, systolic modular multiplier is presented. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Optimal clock rates are attained by virtue of systolic properties of limited fan-out of all signal paths and nearest neighbor interconnections. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations.

REFERENCES:
patent: 5101431 (1992-03-01), Even
patent: 6151393 (2000-11-01), Jeong
patent: 6763365 (2004-07-01), Chen et al.
patent: 6804696 (2004-10-01), Chen et al.
patent: 2004/0010530 (2004-01-01), Freking et al.

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