Systolic computational array

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G06F 1534

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045464456

ABSTRACT:
The present invention provides a systolic computational array including two shift registers. Selected ones of the shift register stages are adapted to provide the values contained therein to two multiply-accumulate devices.

REFERENCES:
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patent: 4392232 (1983-07-01), Andren et al.
patent: 4398274 (1983-08-01), Chotiros
"A CCD Analog and Digital Correlator", Lagnado et al., The International Conference on Charge Couple Devices, Conference Three, 9/76, pp. 238-258.

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