Systolic complex multiplier

Details Systolic complex multiplier Systolic complex multiplier

1985-12-16

1988-09-06

Malzahn, David H.

Boots, shoes, and leggings

364726, G06F 752, G06F 15332, G06F 15347

Patent

active

047697792

ABSTRACT:
A complex multiplier includes a carry-sum systolic array (26) of multiplier cells for processing a multiplicand therethrough in accordance with a modified Booths algorithm. The multiplier performs two multiplications and two addition/substraction operations. A ROM (12) provides the multipliers for the operation which are input to a booth decoder (50) through a delay line (48). The delay line (48) delays pairs of bits by one bit each to synchronize with the flow of the partial products through the array (26). After one product is processed in the array (26), the sum and carry is fed back to the input through a delay (52). This delay allows for processing two products in a single operation with a subsequent operation interleaved therebetween. When one operation is complete, it is output to adders (64) and (66) to perform a complex addition and substraction with another input data vector. This addition occurs at one half the rate of the pipeline (26) due to the interleaving of the two operations.

REFERENCES:
patent: 3800130 (1974-03-01), Martinson et al.
patent: 4228520 (1980-10-01), Letteney et al.
patent: 4275452 (1981-06-01), White
patent: 4344151 (1982-08-01), White
patent: 4546446 (1985-10-01), Machida
patent: 4597053 (1986-06-01), Chamberlin
patent: 4680727 (1987-07-01), White

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