Systolic array image processing system

Image analysis – Histogram processing – For setting a threshold

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395 22, 382 42, G06K 964

Patent

active

051386950

ABSTRACT:
A systolic array of processing elements is connected to receive weight inputs and multiplexed data inputs for operation in feedforward, partially-- or fully-connected neural network mode or in cooperative, competitive neural network mode. Feature vector or two-dimensional image data is retrieved from external data memory and is transformed via input look-up table to input data for the systolic array that performs a convolution with kernal values as weight inputs. The convoluted image or neuron outputs from the systolic array are scaled and transformed via output look-up table for storage in the external data memory.

REFERENCES:
patent: 4546445 (1985-10-01), Haugen
patent: 4559606 (1985-12-01), Jezo et al.
patent: 4737921 (1988-04-01), Goldwasser et al.
patent: 4752897 (1988-06-01), Zoeller et al.
patent: 4758999 (1988-07-01), Marwood et al.
patent: 4760604 (1988-07-01), Cooper et al.
patent: 4769779 (1988-09-01), Chang et al.
patent: 4807183 (1989-02-01), Kung et al.
patent: 4833635 (1989-05-01), McCanny et al.
patent: 4868828 (1989-09-01), Shao et al.
patent: 4885715 (1989-12-01), McCanny et al.
patent: 4893255 (1990-01-01), Tomlinson, Jr.
patent: 4937774 (1990-06-01), Malinowski
patent: 4967340 (1990-10-01), Dawes
Leibowitz, L-M, "Digital Correlator Speed Improvement by Multiplexing", Naval Research Lab, Wash. D.C., Sep. 30, 1983, 44 pages.
Kung, Hwand, "A Unified Systolic Architecture for Artificial Neural Networks", Journal of Parallel and Distributed Computing 6, (1989), pp. 358-387.
LSI Logic-product information brochure (3 pages) "L64240 Multi-bit Filter (MFIR)", Sep. 1989.
LSI Logic-product information brochure (2 pages) "L64210/L64211 variable-Length Video Shift Registers"; Oct. 1989.
Plessey Semiconductors-product information brochure (4 pages) "PDSP16488 Single Chip 2D Convolver With Integral Line Delays"; Sep. 1988.
INMOS-product information brochure (4 pages) "Image and Signal Processing Sub-System"; Jun. 1988.
Provence et al., "Systolic Arrays for Viterbi Processing in Communication Systems With a Time-Dispersive Channel"; IEEE Transactions on Communications, vol. 36, No. 10, Oct. 1988; pp. 1148-1156.
Kim et al., "On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement"; IEEE Transactions on Computers, vol. 38, No. 4, Apr. 1989, p. 516, left-hand column, Para. 5-right-hand column, Para. 1, FIGS. 1-3.
Kung & Hwang, "Parallel Architectures for Artificial Neural Nets" pp. II-165 thru II-172.
Hwang, Kung, et al., "A Universal Digital VLSI Design for Neural Networks", Dept. Electrical Engr., Princeton, pp. 1-8.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Systolic array image processing system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systolic array image processing system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systolic array image processing system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-353427

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.