Boots – shoes – and leggings
Patent
1990-10-04
1993-12-28
Coleman, Eric
Boots, shoes, and leggings
3642712, 364258, 3642582, 3642768, 364DIG1, 364754, G06F 15347
Patent
active
052748324
ABSTRACT:
A multidimensional systolic array processor uses a multidimensional array of systolically coupled processing elements to perform matrix-vector multiplication of matrix and vector signal sets. A two-dimensional array uses a P.times.Q matrix (P rows and Q columns) of processing elements which are coupled to systolically process the signals, e.g. via multiplication and accumulation. The processing elements are coupled both row-to-row and column-to-column for pipeline processing within each row and each column, i.e. multidimensional pipelining, thereby increasing processing parallelism and speed. Interconnectivity of the processing elements is minimized by forming separate column and row signal subsets of the vector signal set which are coupled simultaneously to each processing element in the first row and first column, respectively. Size of the processing elements is minimized by reducing local storage of matrix signal subsets within each processing element. Separate column and row signal subsets of the matrix signal set are formed and coupled into each processing element of the first row and first column, respectively. As the matrix column and row signal subsets are systolically processed and transferred row-to-row and column-to-column, respectively, each signal subset is reduced in size by one signal, thereby requiring the transfer and temporary local storage of successively smaller matrix signal subsets. A three-dimensional processor uses a P.times.Q.times.T array (T planes of P rows and Q columns) of processing elements which are coupled plane-to-plane-to-plane.
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S. Y. Kung & J. N. Hwang, "Parallel Architecture for Artificial Neural Nets," IJCNN, 1989, pp. II-165-II-172.
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Coleman Eric
National Semiconductor Corporation
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