Systolic array for modular multiplication

Details Systolic array for modular multiplication Systolic array for modular multiplication

1990-12-14

1992-03-31

Gregory, Bernarr E.

Cryptography

Particular algorithmic function encoding

Public key

380 28, 364746, 3647461, H04L 930, G06F 752, G06F 772

Patent

active

051014319

ABSTRACT:
A systolic array (10) comprising a sequence of identical cells is utilized to perform modular reduction in linear time. Each cell receives a binary number at a first input and an n-bit modulus at a second input and performs binary addition to form a binary number output. The systolic array (10) for performing modular reduction may be combined with Atrubin's array (60) to perform modular multiplication.

REFERENCES:
"A Survey of Hardware Implementations of RSA", E. F. Brickell, presented at CRYPTO '89, Santa Barbara, Calif., Aug. 1989.
"A Cryptographic Library for the Motorola DSP 56000", S. R. Dusse et al., EuroCrypt 90--Abstracts, May 21-24, 1990, Scantic on Arhus, Denmark, pp. 230-244.
"VICTOR, An Efficient RSA Hardware Implementation", H. Orup et al., EuroCrypt 90--Abstracts, May 21-24, 1990, Scanticon Arhus, Denmark, pp. 245-252.
"A One-Dimensional Real Time Iterative Multiplier", A. J. Atrubin, IEEE Trans. on Electronic Computers, vol. 14, pp. 394-399, 1965.
"Modular Multiplication Without Trial Division", P. L. Montgomery, Math. of Computation, vol. 44, pp. 519-521, 1985.

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