Systolic architecture for computing an inverse discrete wavelet

Details Systolic architecture for computing an inverse discrete wavelet Systolic architecture for computing an inverse discrete wavelet

1998-08-06

2000-04-04

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 1500

Patent

active

060473037

ABSTRACT:
The invention provides an integrated systolic architecture which can perform both forward and inverse Discrete Wavelet Transforms with a minimum of complexity. A plurality of processing cells, each having an adder and a multiplier, are coupled to a set of multiplexers and delay elements to selectively receive a single input datastream in the forward DWT mode and two datastreams in the inverse DWT mode. In the forward DWT mode, the integrated architecture decomposes the input datastream into two output sequences--a high frequency sub-band output and a low frequency sub-band output. In the inverse DWT mode, the integrated architecture reconstructs the original input sequence by outputting even terms and odd terms on alternating clock cycles. As a result, the architecture can achieve 100% utilization and is suitable to be implemented in VLSI circuitry.

REFERENCES:
patent: 5602589 (1997-02-01), Vishwanath et al.

Affiliated with

Also associated with

Rating

Systolic architecture for computing an inverse discrete wavelet does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systolic architecture for computing an inverse discrete wavelet , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systolic architecture for computing an inverse discrete wavelet will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-374339