Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-05-03
2003-07-22
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185140, C365S185180, C365S236000, C365S239000
Reexamination Certificate
active
06597605
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to non-volatile programmable memory, and specifically to programming an array of electrically programmable non-volatile memory cells.
2. Background Information
Non-volatile programmable memories are well known. One of the earliest non-volatile programmable memories were one time programmable (OTP) memory cells which used a diode or transistor with a fuse or an antifuse to program the cell to indicate a logical one or a logical zero when the cell was addressed. Another initially one time programmable memory cell was an electrically programmable read only memory (EPROM) cell. The EPROM was a transistor that was electrically programmable by storing a trapped charge underneath its gate. The trapped charge underneath the gate changed the gate to source threshold voltage of the EPROM. The gate to source threshold voltage was the voltage level above which the EPROM transistor would turn on to conduct a current between its source and drain. The EPROM cell later became erasable by using ultraviolet light radiating through windows in an integrated circuit to reduce or remove the trapped charge so the threshold voltage would return to normal. The UV erasing of the EPROM cell allowed it to be multiprogrammable. However, UV erasing required removal of the integrated circuit from a printed circuit board. To avoid the UV erasing, an electrically erasable programmable read only memory (EEPROM) cell was introduced. The EEPROM memory cell made it possible to program while it remained in circuit on the printed circuit board. In order to be both electrically erasable and programmable, the EEPROM cell included a transistor that uses a floating gate to store a charge. A charge pump triggered upon programming or erasing was needed in the same circuit to generate a high voltage to apply or erase a trapped charge onto or from a floating gate of an EEPROM cell. For a given voltage level, a programming time period is required that is needed to store and erase the charge from the floating gate. Over an array of memory cells this programming time can become significant causing other circuits to wait which delayed the return to functionality of a system.
To reduce the programming time of an array of non-volatile programmable memory cells, it is desirable to program as many EEPROM cells in parallel together as possible. However, there is a limit to the current that can be supplied by a given charge pump. Because programming the EEPROM cell requires a relatively high programming voltage and current to form the trapped charge, the available charge pump current limits how many cells can be programmed in parallel together.
It is desirable to reduce the programming time of an array of non-volatile programmable memory cells and more efficiently program an integrated circuit containing non-volatile programmable memory cells.
REFERENCES:
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5280447 (1994-01-01), Hazen et al.
patent: 5379413 (1995-01-01), Hazen et al.
patent: 5414669 (1995-05-01), Tedrow et al.
patent: 5414829 (1995-05-01), Fandrich et al.
patent: 5430674 (1995-07-01), Javanifrad
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5537350 (1996-07-01), Larsen et al.
patent: 5546410 (1996-08-01), Ando
patent: 5815443 (1998-09-01), Sweha et al.
patent: 5907700 (1999-05-01), Talreja et al.
patent: 5910180 (1999-06-01), Flory et al.
patent: 5937424 (1999-08-01), Leak et al.
patent: 5954818 (1999-09-01), Dalvi et al.
patent: 5966723 (1999-10-01), James et al.
patent: 6418059 (2002-07-01), Kreifels et al.
V. Siva Kumar, OTP EPROMs with Quick-Pulse Programming offer ideal mass production firmware storage, Memory Components Handbook, Intel Corporation, 1989, p 4-373-4-375.
S. Zales & D. Elbert, Using the 28F256 Flash Memory for In-System Reporgrammable Nonvolatile Storage, Memory Components Handbook, Intel 1989, p 5-89-5-122.
Elbert, Nogo & Zales, The 27F64 Flash Memory—Your Solution for On-Board Programming, Memory Components Handbook, Intel Corporation, 1989, p 5-79-5-87.
Intel Corporation, 64K (8K×8) CHMOS Flash Memory, Memory Components Handbook, Intel Corporation, 1989, p 5-15 -5-35.
K. Robinson, Using Simple Circuits, Algorithms to Program 521k-bit EPROMS, Memory Components Handbook, Intel Corporation, 1989, p 4-354-359.
Johnson, Kuh, Renninger & Perlegos, 16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage, Memory Components Handbook, Intel Corporation, 1989.
Knowlton, Versatile Algorithm, Equipment Cut EPROM Programing Time, Memory Components Handbook, Intel Corporation, 1989, p 4-12-4-16.
Davis, Programming Intel's 27256 EPROM, Memory Components Handbook, Intel Corporation, 1989, p 4-2-4-5.
Intel Corporation, 16K (2K×8) Electrically Erasable PROM, Memory Components Handbook Intel Corporation, 1989, p 5-95-5-103.
M. Vanbuskirk, et al., E-PROMs Graduate to 256-K Densit with Scaled N-Channel Process, Memory Components Handbook, Intel Corporation, 1989, P 4-6 -4-11.
Intelcorporation, 16K (2K×8) Electrically Erasable PROM, Memory Components Handbook, Intel Corporation, 1989 p 5-83-5-94.
Dorf, Nonvolatile Programmable Memories, The Electrical Engineering Handbook, CRC Press, Florida, p 1654-1655, 1993.
Prince, EPROM Memory Cell: Floating Gate Avalanche Injection MOS, Semiconductor Memories, John Wiley & Sons, West Sussex, England, 1991, p 102-103.
Prince, Overview of Non-Volatile MOS Memories, Semiconductor Memories, John Wiley & Sons, West Sussex, England, 1991, p 142-187.
Prince, Field Alterable ROMs I: EPROM, OTP, and Flash Memories, Semiconductor Memories, John Wiley & Sons, West Sussex, England, 1991 p 529-608.
Prince, Field Alterable ROMs II: EEPROM, EAROM, NV-RAM, Semiconductor Memories, John Wiley & Sons, West Sussex, England, 1991, p 609-662.
Kreifels Jerry A.
Rozman Rodney R.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Viet Q.
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