Systems for testing integrated circuits

Details Systems for testing integrated circuits Systems for testing integrated circuits

2001-03-30

2003-04-01

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754090, C324S761010

Reexamination Certificate

active

06541990

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to integrated circuits and, in particular, to testing systems that may be utilized for testing integrated circuits.
2. Related Art
The proliferation of integrated circuits (IC's) has lead to the development of numerous IC testing procedures. In accordance with a conventional testing procedure, an IC is temporarily mounted to a circuit assembly, such as a printed circuit board is (PCB), for example. So mounted, electrical communication is facilitated between at least one pad or pin of the IC and test equipment. Typically, the test equipment is configured to evaluate operational parameters of the IC. Thus, mounting of the IC to the circuit assembly enables testing of the IC in an operational environment as the pins of the IC electrically communicate with respective contacts or traces of the PCB as well as with the test equipment.
As is known, the ability of a particular testing procedure to provide accurate testing information relies, at least in part, on the ability of the procedure to facilitate proper electrical communication between the IC's to be tested and the test equipment. However, the structural demands associated with repetitive IC testing has, oftentimes, resulted in testing procedures and associated testing devices that provide less than desired performance characteristics.
SUMMARY
Briefly described, the invention relates to testing of integrated circuits (IC's). In this regard, some embodiments of the invention may be implemented as an IC testing system that includes a test array. The test array is configured to enable testing of a device under test (DUT), e.g., an IC, by facilitating electrical communication of the pins of the IC with test equipment. This is accomplished while the IC is electrically interconnected to a circuit assembly, e.g., a printed circuit board.
A representative example of the test array incorporates a frame, with the frame defining an aperture that is appropriately sized and shaped for receiving a DUT. The frame also mounts one or more testing probes that are adapted to extend into the aperture so as to be appropriately positioned for electrically engaging the DUT. The probes preferably are received within recesses formed along a bottom surface of the frame. This configuration tends to enable the bottom surface of the frame to properly engage a surface to which it is to be mounted, e.g., a surface of a PCB.
Engagement of the probes within the recesses also facilitates proper positioning of the probes. More specifically, one or more of the probes may incorporate a configuration that tends to maintain the position of the probes relative to the frame and, thus, relative to the aperture. For instance, one or more of the probes may include an S-shaped portion (S-shaped when viewed in a plan view), a circular portion (circular when viewed in a plan view), or various other shaped portions intermediately disposed along the length of each probe. So configured, when the shaped portion of the probe is received within a corresponding complimentary-shaped portion of its respective recess, the probe is substantially prevented from being urged along its longitudinal axis. More specifically, the various surfaces defining the shaped portion of the recess function as mechanical stops for substantially preventing movement of the probe.
In some embodiments of the testing system, controllers for providing a test signal to a DUT and receiving test information corresponding to the DUT are provided. Additionally, some embodiments incorporate a seating mechanism that is configured to engage a DUT with the test array so that the pins of the DUT electrically engage the test probes of the test array.
Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional system, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.


REFERENCES:
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patent: 4329642 (1982-05-01), Luthi et al.
patent: 4554505 (1985-11-01), Zachry
patent: 5729147 (1998-03-01), Schaff
patent: 6094057 (2000-07-01), Hiruta et al.
Aries Electronics, Inc., High Performance, RF Test Sockets (featuring the patented microstrip Contact), (month unavailable) 1997.

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