Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-08-08
2003-01-21
Wells, Kenneth B. (Department: 2816)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S254000
Reexamination Certificate
active
06509794
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention generally relates to the field of amplifiers, and more particularly, to rail-to-rail dynamically controlled amplifiers and input stages.
2. Background Information
With the logical progression toward lower voltage supplies and lower power electronics comes the need for analog components that can provide the same electrical performance as their older higher voltage counterparts. One extremely important aspect is the ability to handle voltage levels as close to and including each supply rail. This allows for maximum signal swing for a given supply voltage, which helps improve performance aspects of signal-to-noise ratio, linearity, and flexibility of interconnection.
U.S. Pat. No. 4,555,673 entitle d “Differential Amplifier with Rail-to-Rail Input Capability and Controlled Transconductance,” issued on Nov. 26, 1985 to Johan H. Huijsing and Rudy J. van de Plassche, discloses a circuit 100 that provides rail-to-rail operation while maintaining overall amplifier gain through indirect means. As shown in
FIG. 1
, such a circuit
100
includes two complementary difference amplifiers
102
and
104
, where difference amplifier
102
consists of a differential pair of transistors Q
1
. and Q
2
, and difference amplifier
104
consists of a differential pair of transistors Q
3
and Q
4
. Each differential amplifier may have an associated current source. The differential amplifiers are attached to a clamp device
106
, formed by transistors Q
N
and Q
P
.
When the voltage of the common mode input approaches the level of a supply voltage, one of the difference amplifiers, e.g. difference amplifier
102
, can collapse its associated current source. In such a case, clamp device
106
shuts off that particular difference amplifier
102
and accordingly shuts down its normal output signals. The current from clamp device
106
is then rerouted to bias circuitry for the other difference amplifier, e.g. difference amplifier
104
. The bias of difference amplifier
104
is therefore doubled, which in turn doubles that amplifier's gain and corrects for the loss of gain from the other difference amplifier
102
. This is the case, however, only if the two complementary difference amplifier outputs are summed together.
One disadvantage to this configuration is that it can impose limitations on the down stream circuitry. Another disadvantage is the net change in input bias current. Typically the net change is around two to four times the value present when both difference amplifiers are in the “on” state. The shut down operation can cause a one hundred percent change in bias current. Increasing the bias for the opposite stage can increase that change by an additional one hundred to three hundred percent or more. With both difference amplifiers
102
and
104
in the “on” state their input bias currents, for bipolar devices, can partially cancel since they are of opposite polarity. When one side is shut off, the partial cancellation stops and becomes the full value of the “on” side's base current. By increasing the “on” side's bias current the base current will also go up.
U.S. Pat. No. 5,294,892 entitled “Two-stage Rail-to-Rail Class AB Operational Amplifier,” issued Mar. 15, 1994 to Marc H. Ryat, discloses that the current source used to bias the complementary differential pairs is allowed to shut off. No provision is made to correct for the gain change that this causes.
U.S. Pat. No. 5,311,145 entitled “Combination Driver-Summing Circuit for Rail-to-Rail Differential Amplifier,” issued May 10, 1994 to Johan H. Huijsing and John P. Tero, discloses a traditional input stage of an amplifier that can employ a scheme very similar to U.S. Pat. No. 4,555,673. This arrangement is simpler in its approach in that it may only have one differential pair on at a time. Since it can be implemented in CMOS (complementary metal oxide semiconductor), it may not suffer the input bias current shift, but it can impose some restrictions on down stream circuitry.
U.S. Pat. No. 5,414,388 entitled “Rail-to-Rail Operational Amplifier Input Stage,” issued May 9, 1995 to Don R. Sauer, also discloses an input bias control method that is similar to U.S. Pat. No. 4,555,673. One similarity is that the current in the complementary differential pair can be turned up when the current falls in the other differential pair. One difference, however, is that the current drive to either input pair can be automatically shut off using an additional differential pair for each input pair. The secondary differential pairs can be used to channel the main bias current directly to their associated input pair, or to the current source circuitry for the opposite input differential pair. This stacking of stages can deeply cut into the available supply voltage which makes this scheme not preferable in very low voltage applications. This scheme also relies on a saturation effect to perform its functions, which can cause some recovery problems that may show up as undesirable anomalies or glitches in waveforms during switching transitions.
Accordingly, there is a need for an operational amplifier design that can imp rove upon the limitations of known amplifiers.
SUMMARY
The limitations of known systems have been substantially improved upon by the present invention.
According to an embodiment of the invention, a rail-to-rail dynamically controlled amplifier circuit comprises a first difference circuit and a second difference circuit. The first difference circuit includes a first primary pair of transistors, a first crossover pair of transistors running in parallel with the first primary pair of transistors, a first level shifting circuit wherein the output of the first primary pair is coupled to control electrodes of the first level shifting circuit, and a first current source coupled to the first primary pair of transistors and the first crossover pair of transistors. The second difference circuit includes a second primary pair of transistors, a second crossover pair of transistors running in parallel with the second primary pair of transistors, a second level shifting circuit wherein the output of the second primary pair is coupled to control electrodes of the second level shifting circuit, and a second current source coupled to the second primary pair of transistors and the second crossover pair of transistors.
This embodiment of the amplifier circuit further comprises an upper voltage supply and a lower voltage supply coupled to the first difference circuit and the second difference circuit, and a pair of input lines wherein the input lines are coupled to control electrodes of the first primary pair of transistors and control electrodes of the second primary pair of transistors. In addition, the first level shifting circuit is coupled to control electrodes of the second crossover pair of transistors, and the second level shifting circuit is coupled to control electrodes of the first crossover pair of transistors.
In accordance with another embodiment of the invention, a method for amplifying a rail-to-rail input signal begins by providing a differential amplifier circuit that includes a first primary differential amplifier, a first crossover differential amplifier, a second primary differential amplifier, and a second crossover differential amplifier, wherein the polarity of the first primary differential amplifier and the first crossover differential amplifier is opposite that of the second primary differential amplifier and the second crossover differential amplifier. The method then comprises receiving and amplifying an input differential signal with a voltage that fluctuates between a first value slightly above an upper supply rail and a second value slightly below a lower supply rail.
According to this embodiment, when the voltage of the input differential signal is within a middle region of operation, defined as a voltage region that is about midway between the upper supply rail and the lower supply rail but not relatively close to either supply rail, the method comprises amplifyi
Cox Cassandra
Fairchild Semiconductor Corporation
Skjerven Morrill LLP
Wells Kenneth B.
Woo Philip W.
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