Systems for interconnecting and configuring plurality of memory

Details Systems for interconnecting and configuring plurality of memory Systems for interconnecting and configuring plurality of memory

1990-03-21

1992-09-08

Lee, Thomas C.

Boots, shoes, and leggings

3642292, 3642319, 3642421, 364243, 36493141, 364964, 36494052, 36424296, 364DIG1, G06F 1516

Patent

active

051466066

ABSTRACT:
An array processing system including a plurality of processing elements each including a processor and an associated memory module, the system further including a router network over which each processing element can transfer messages to other random processing elements, a mechanism by which a processor can transmit data to one of four nearest-neighbor processors. In addition, the processing elements are divided into groups each with four processing elements, in which one of the processing elements can access data in the other processing elements' memory modules. The routing network switches messages in a plurality of switching stages, with each stage connecting to the next stage through communications paths that are divided into groups, each group, in turn being associated with selected address signals. A communications path continuity test circuit associated with each path detects any discontinuity in the communications path and disables the path. Thus, the stage may attempt to transfer a message over another path associated with the same address.

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