Systems and methods for testing integrated circuits

Details Systems and methods for testing integrated circuits Systems and methods for testing integrated circuits

2003-02-19

2004-03-16

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06707313

ABSTRACT:

BACKGROUND
Efficient testing of integrated circuits (ICs) has become increasingly difficult due to increased density of the ICs. Attributes of increased IC density include an increased distribution of logic located within a single IC to enable performance of an increased number of functions via use of the IC.
A goal of IC testing is to verify that each IC has been manufactured without defects. At a high level, IC testing may be viewed as coupling the IC to a host system and determining whether the host system appears to be functioning normally while running an application that utilizes the IC. If the host system functions normally, then a determination is made that the IC is ready to be shipped. However, this type of system-level test does not ensure that the IC is defect-free since the given applications used to test the IC may merely exercise a subset of functionality made available by the IC.
Thorough testing of ICs requires the application of test patterns with very high fault coverage. As is known, faults are logical abstractions of physical defects that result in errors received during testing of an IC, or during use of the IC. Examples of faults include, but are by no means limited to, stuck-at, transition, path delay, and bridging faults. Fault coverage of a set of test patterns is a measure of a percentage of possible faults that are detected by the test patterns. For a large and complex IC (i.e., a high density IC), the task of creating a set of patterns that provide full fault coverage can be very difficult and time consuming. Specifically, the sequential depth of circuitry embedded within the IC, in addition to a very large logic-to-pin ratio, results in pin-based functional testing being prohibitive due to time requirements associated with testing and demands on test resources.
Due to the above difficulties, most ICs are tested using structured design-for-testability (DFT) techniques. DFT techniques utilize the general concept of selecting a portion or all digital circuit elements within an IC, such as flip-flops and logic gates, that are directly controllable and observable within the IC. An example of a commonly used DFT technique is scan design, in which flip-flops are serially linked together in scan chains. During testing, data is shifted serially into the flip-flops located along the scan path while the IC is in a test mode. The flip-flops are then clocked one or more times while the IC is in a normal mode, thereby capturing the resulting response of the logic gates located within the IC to the final scanned-in state stimulus. The captured data is serially shifted out of the IC while in the test mode. Data captured during IC scan testing is analyzed by test equipment located external to the IC as the data is shifted out of the IC, thereby determining whether a correct response was obtained for each IC test stimulus. This style of testing is known as “structural testing,” as opposed to “functional testing,” which is performed through pins of the IC while the IC is in normal mode.
To create a structural test for an IC, a software tool referred to as an automatic test pattern generator (ATPG) utilizes a simulation model of the IC that includes the scan flip-flops and combinational logic of the IC, as well as a target fault model that represents a specific class of defects. When applied to the simulation model of a given IC, the target fault model results in a list of specific faults, also referred to as a target fault list, for which test patterns are to be generated. A deterministic ATPG superimposes each fault within the target fault list on the simulation model of the IC in order to guide the creation of a specific test pattern, also referred to as a test vector, that is intended to expose the superimposed fault. The ATPG generates test patterns for each location in the IC model at which a fault, and thereby an associated defect, could exist. Each test pattern is a set of 1s and 0s that are necessary to excite and propagate the hypothesized fault to an observation point (i.e., a scannable flip-flop), as well as the expected response of a defect-free IC. If an IC responds to a test pattern with data other than that expected, then the hypothesized fault is deduced to be present and the IC is considered to be defective.
Typically, a complete set of test patterns is intended to cover all possible faults in an IC, thereby achieving full fault coverage. For high density ICs, the number of faults that require consideration during ATPG can be quite substantial. As such, attempts at ATPG can create large numbers of test patterns, each of which typically detects only a small number of faults. Such inefficiencies could delay the completion of an IC chip design project and/or slow time-to-market of an IC. Furthermore, such inefficient testing can require high tester memory and longer test application time, thereby increasing cost of the IC.
SUMMARY
Systems and methods for testing integrated circuits are provided. An embodiment of a method comprises: providing a target fault list corresponding to an integrated circuit, the target fault list including at least a first fault and a second fault; measuring a relationship between the first fault and the second fault, the relationship corresponding to which of the first fault and the second fault is more readily detected by automatic test pattern generation; ordering the first fault and the second fault within the target fault list in a manner corresponding to the relationship; and performing automatic test pattern generation based upon an order of the faults of the target fault test.
An embodiment of a system comprises: a memory operative to store information corresponding to a target fault list of an integrated circuit, the target fault list including at least a first fault and a second fault; and a processor communicating with said memory, the processor being operative to measure a relationship between the first fault and the second fault, the relationship corresponding to which of the first fault and the second fault is more readily detected by automatic test pattern generation, to order the first fault and the second fault within the target fault list in a manner corresponding to the relationship, and to perform automatic test pattern generation based upon an order of the faults of the target fault test.
Computer-readable media also are provided that include computer programs for providing integrated circuit test pattern generation. An embodiment of a computer-readable medium comprises: logic configured to provide a target fault list corresponding to an integrated circuit, the target fault list including at least a first fault and a second fault; logic configured to measure a relationship between the first fault and the second fault, the relationship corresponding to which of the first fault and the second fault is more readily detected by automatic test pattern generation; logic configured to order the first fault and the second fault within the target fault list in a manner corresponding to the relationship; and logic configured to perform automatic test pattern generation based upon an order of the faults of the target fault test.


REFERENCES:
patent: 5521516 (1996-05-01), Hanagama et al.
patent: 6067651 (2000-05-01), Rohrbaugh et al.

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