Systems and methods for refreshing non-volatile memory

Details Systems and methods for refreshing non-volatile memory Systems and methods for refreshing non-volatile memory

2002-04-24

2004-06-15

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185330

Reexamination Certificate

active

06751127

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile, rewritable memory and in particular, to methods and systems for refreshing non-volatile, rewritable memory arrays.
2. Description of the Related Art
In a typical FLASH memory array, the memory cells are arranged in a rectangular array of rows and columns to form intersections at which there are disposed memory cell transistors. The drain of each transistor is connected to a corresponding bit line, the source of each transistor is connected to an array source voltage by an array source line, and the gate of each transistor is connected to a wordline.
Typical FLASH memories allow cells to programmed, read or erased in bulk, sectors or pages. In addition, some FLASH memories can be operated in an EEPROM mode, where from the user perspective, cells can be programmed, read or erased on a byte basis. Cells are conventionally programmed by driving selected bit lines connected to the memory cell transistor drains to a first voltage and driving the gates of the memory cell transistors connected to selected wordlines to a second higher voltage to perform hot electron injection.
The erasure of FLASH memory cell data is performed by driving the gate of a memory cell transistor to a voltage that is substantially less than a voltage placed on the bit line. In doing so, electrons are tunneled off of the floating gate of the memory cell transistor. By way of example, the erase operation can be performed as a bulk erase, which erases the entire FLASH memory array, a sector erase, which erases a FLASH memory array sector, or a page erase, which erases a single sector row. If the FLASH memory can be operated in an EEPROM mode, then the erasure can, from the user perspective, be performed on a byte basis.
However, FLASH memories are subject to a disturb phenomenon during erase and program operations. Because memory cells may share the same bit lines across sectors, voltages placed on these bit lines produce electrical field effects on the sectors sharing the bit lines. Furthermore, memory cells within different sectors may share wordlines, and voltages on these shared wordlines create field effects in the sectors sharing them.
The electric fields generated on the shared bit lines and wordlines may have the effect of inadvertently erasing programmed bits or programming erased bits. For example, raising the voltage on a wordline to program an erased bit may disturb a previously programmed bit on the same wordline by removing some electrons from the floating gate to the control gate of the previously programmed bit. Thus, the sector cells need to be refreshed after each erase or program operation or after a predetermined number of erase or program cycles.
One conventional technique for performing refresh operations is to perform a refresh on an entire sector after each erase/program operation, where the contents of the sector to be refreshed are buffered and then rewritten. However, the buffer used to store the sector contents utilizes a significant amount of area and so the sector size may need to be constrained to reduce the buffer size. Another conventional technique for determining when to perform a refresh operation is to count the number of erase or program cycles using a counter, and performing a refresh after a predetermined number of cycles. However, such counters are often of insufficient reliability. Hence these conventional refresh techniques fail to provide a refresh process that is both efficient and reliable.
SUMMARY OF THE INVENTION
The present invention is directed to methods and systems for refreshing non-volatile memories, such as FLASH memories that can be operated in an EEPROM mode. In particular, one embodiment of the present invention embeds a refresh process in a write operation. After each program/erase cycle, a refresh operation is performed beginning at the byte cells associated with the selected bit line and proceeding sequentially. In one embodiment, a cell current is measured, and if the cell current meets a first criteria, the cell is refreshed.
In particular, a predetermined amount of time is allocated for performing a refresh process, including both the actual refresh and a verify process. Using an embodiment of the present invention, if the cells associated with a wordline can sustain more than N cycles without needing to be refreshed, then 1/N sectors can be sequentially refreshed after each erase or program operation. This is in contrast to some conventional techniques that refresh an entire sector after each erase or program operation. Advantageously, the present invention reduces the size needed for a refresh buffer and enables enlargement of the sector size by a factor N, without use of a refresh cycle counter.
In particular, a write or rewrite operation includes 3 embedded operations: an erase operation, a program operation, and a refresh operation. During the refresh operation, a FLASH cell floating gate is charged using Channel Hot Electron injection (CHE) by providing a high bias on the gate and an elevate bias on the drain. In one embodiment, a cell is refreshed when the cell current falls within a predetermined range. Thus, rather then refreshing every cell within a sector when performing a refresh operation, the refresh operation is performed on those cells whose cell current falls within a predetermined range.


REFERENCES:
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patent: 5765185 (1998-06-01), Lambrache et al.
patent: 5909449 (1999-06-01), So et al.
patent: 6088268 (2000-07-01), Gupta et al.
patent: 6240032 (2001-05-01), Fukumoto

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