Systems and methods for reducing circuit area

Details Systems and methods for reducing circuit area Systems and methods for reducing circuit area

2007-11-20

2010-12-07

Nguyen, Tuyen (Department: 2832)

Inductor devices

Coil or coil turn supports or spacers

Printed circuit-type coil

Reexamination Certificate

active

07847667

ABSTRACT:
Methods and systems are provided for reducing circuit area. Some embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path crosses itself at least two points and wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane. Other embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane, and wherein the circuit comprises a signal path that is rake-shaped and crosses the path of the inductor at substantially perpendicular angles.

REFERENCES:
patent: 6072205 (2000-06-01), Yamaguchi et al.
patent: 6437653 (2002-08-01), Cruz et al.
patent: 6486529 (2002-11-01), Chi et al.
patent: 6775901 (2004-08-01), Lee et al.
patent: 6825749 (2004-11-01), Lin et al.
patent: 6856225 (2005-03-01), Chua et al.
patent: 6870457 (2005-03-01), Chen et al.
patent: 6885275 (2005-04-01), Chang
patent: 6940355 (2005-09-01), Hajimiri et al.
patent: 7088195 (2006-08-01), Muramatsu et al.
patent: 2003/0202331 (2003-10-01), Jessie et al.
patent: 2003/0222732 (2003-12-01), Matthaei
patent: 2008/0180187 (2008-07-01), Kinget et al.
patent: 499828 (2002-08-01), None
International Search Report and Written Opinion for International Patent Application No. PCT/US2006/020155.
R. Ahola et al., “A single-chip CMOS transceiver for 802.11a/b/g wireless LANs,”IEEE J. Solid-State Circuits, vol. 39, No. 12, pp. 2250-2258, Dec. 2004.
C.-L. Chen, “Effects of CMOS process fill patterns on spiral inductors,”Microw. Opt. Technol. Lett., vol. 36, pp. 462-465, 2003.
C. Detcheverry, “The effect of copper design rules on inductor performance,” inProc. Eur. Solid-State Device Research Conf., Sep. 2003, pp. 107-110.
E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,”IEEE J. Solid-State Circuits, vol. 36, No. 12, pp. 1921-1930, Dec. 2001.
S. Kapur and D. E. Long, “Large-scale full-wave simulation,” inProc. Design Automation Conf., Jun. 2004, pp. 806-809.
P. Kinget, “Integrated GHz voltage controlled oscillators,” inAnalog Circuit Design: (X)DSL and Other Communication Systems; RF MOST Models; Integrated Filters and Oscillators,W. Sansen, J. Huijsing, and R. van de Plassche, Eds. Boston, MA: Kluwer, 1999, pp. 353-381.
W. B. Kuhn et al., “Spiral inductor performance in deep-submicron bulk-CMOS with copper interconnects,” inIEEE MTT-S Int. Microwave Symp. Dig., Jun. 2002, vol. 1, pp. 301-304.
Cover photograph of: T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 1st ed. Cambridge, U.K.: Cambridge Univ. Press, 1998.
R. G. Meyer, “Low-power monolithic RF peak detector analysis,”IEEE J. Solid-State Circuits, vol. 30, No. 1, pp. 65-67, Jan. 1995.
Y. Papananos and N. Nastos, “Inductor over MOSFET: Operation and theoretical study of a CMOS RF three-dimensional structure,” inProc. 24th Int. Conf. Microelectronics, May 2004, pp. 525-529.
C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned ground shields for Si-based RF ICs,”IEEE J. Solid-State Circuits, vol. 33, No. 5, pp. 743-752, May 1998.
F. Zhang, C.-F. Chu, and P. Kinget, “Voltage-controlled oscillator in the coil,” inProc. IEEE Custom Integrated Circuits Conf., Sep. 2005, pp. 587-590.
F. Zhang and P. Kinget, “Design of Components and Circuits Underneath Integrated Inductors,”IEEE Journal of Solid-State Circuits, Oct. 2006, pp. 2265-2271.
F. Zhang, Chen-Feng Chu and P. Kinget, “Voltage-controlled oscillator in the coil,” Slides presented at the IEEE Custom Integrated Circuits Conference (CICC),Oct. 2005.
International Search Report and Written Opinion issued for corresponding International Application No. PCT/US2006/020155.
Da Dalt, Nicola, et al., “A 10b 10GHz Digitally Controlled LC Oscillator in 65 nm CMOS,” Digest of Technical Papers International Solid-State Circuits Conference, pp. 669-678, Feb. 2006.
Josse, E., et al., “A Cost-Effective Low Power Platform for the 45-nm Technology Node,” International Electron Devices Meeting (IEDM), pp. 1-4, Dec. 11-13, 2006.
Kinget, P., B. Soltanian, S. Xu, S. Yu and F. Zhang, “Advanced Design Techniques for Integrated Voltage Controlled LC Oscillators,” IEEE Custom Integrated Circuits Conference, pp. 805-811, Sep. 2007.
Rylyakov, A.V., et al., “A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI,” Digest of Technial Papers International Solid-State Circuits Conference, pp. 172-173, Feb. 2007.
Staszewski, R., et al., “All-digital PLL and GSM/EDGE transmitter in 90nm CMOS,” Digest of Technical Papers IEEEE International Solid-State Circuits Conference (ISSCC), pp. 316-317, Feb. 2005.
Suehle, J.S., “Ultrathin Gate Oxide Reliability: Physical Models, Statistics, and Characterization,” IEEEE Transactions on Electron Devices, vol. 49, No. 6, pp. 985-971, Jun. 2002.
Yu, S.A. and P. Kinget, “A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC), pp. 304-305, Feb. 2007.
Yu, S.A. and P. Kinget, “A 0.042-mm2 Fully Integrated Analog PLL with Stacked Capacitor-Inductor in 45nm CMOS,” European Solid-State Circuits Conference, pp. 94-97, Sep. 2008.
Balankutty et al., “A 0.6V 32.5mW Highly Integrated Receiver for 2.4 GHz ISM-Band Applications,” 2008 IEEE International Solid-State Circuits Conference, pp. 366, 367, and 620, 2008.
Yu et al., “A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS,” 2007 IEEE International Solid-State Conference, pp. 304, 350, and 604, 2007.
Kossel et al., “A Low-Jitter Wideband Multiphase PLL in 90nm SOI CMOS Technology,” 2005 International Solid-State Circuits Conference, pp. 414 and 415, 2005.
Gebara et al., “A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology,” 2007 IEEE International Solid-state Conference, pp. 312 and 313, 2007.
Desai et al., “A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process,” 2007 IEEE International Solid-State Conference, pp. 308, 309, and 604, 2007.
Weltin-Wu et al., “A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction,” 2008 IEEE International Solid-State Conference, pp. 344, 345, and 618, 2008.
Borremans, “A 400uW 4.7-to-6.4GHz VCO under an Above-IC Inductor in 45nm CMOS,” 2008 IEEE International Solid-State Conference, pp. 536, 537, and 634, 2008.
Long et al., “The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's,” IEEE Journal of Solid-State Circuits, vol. 32, No. 3, Mar. 1987.
U.S. Appl. No. 12/491,608, filed Jun. 25, 2009, in which prosecution is on-going.
U.S. Appl. No. 60/684,496, filed May 24, 2005.
U.S. Appl. No. 61/075,403, filed Jun. 25, 2008.

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