Systems and methods for reconfigurable computing

Details Systems and methods for reconfigurable computing Systems and methods for reconfigurable computing

2005-01-21

2010-02-23

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C710S104000, C712S013000

Reexamination Certificate

active

07669035

ABSTRACT:
A processing system includes a communication bus. a controller, an Input/Output (“I/O”) block, and reconfigurable logic segments (e.g., reconfigurable units). Individually reconfigurable logic segments are part of a single chip. A communication bus is in electrical communication with the logic segments. A first logic segment communicates to a Second logic segment over the communication bus. Reconfiguration can partition a first logic segment into a second and a third logic segment where the smaller logic segments are in electrical communication with the communication bus. Resources are dynamically reallocated when reconfigurable units are either combined or partitioned. More specifically, both partitioning a logic segment and combining two or more logic segments can change the bus width allocated to a reconfigurable unit and the quantity of logic gates in the reconfigured unit. As a result of a reconfiguration, a logic segment's embedded resources can change. The processing system provides high chip utilization throughout the chip's operation.

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