Systems and methods for programming floating-gate transistors

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Reexamination Certificate

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C365S185050, C365S185230

Reexamination Certificate

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11382640

ABSTRACT:
A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected to each floating-gate within the row, while each column of transistors includes a column programming switch having an output connected to each drain within the column. The source of each transistor is coupled with a source line corresponding to the specific row of the transistor. The row and column programming switches are utilized to select and program a desired floating-gate transistor. In an indirect programming method, two transistors share a floating gate, such that programming a programmer transistor modifies the current of an agent transistor, which is attached to the circuit, thereby permitting run-time programming.

REFERENCES:
patent: 4486769 (1984-12-01), Simko
patent: 5172196 (1992-12-01), Matsukawa et al.
patent: 6064595 (2000-05-01), Logie et al.
patent: 6295226 (2001-09-01), Yang
patent: 6300662 (2001-10-01), Doyle et al.
patent: 1 096 502 (2001-05-01), None

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