Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2008-06-06
2010-02-02
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000
Reexamination Certificate
active
07656340
ABSTRACT:
Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.
REFERENCES:
patent: 5072221 (1991-12-01), Schmidt
patent: 5272701 (1993-12-01), Tsuruoka
patent: 5296856 (1994-03-01), Mantong
patent: 5861829 (1999-01-01), Sutardja
patent: 6002356 (1999-12-01), Cooper
patent: 6081219 (2000-06-01), Prasanna
patent: 6373423 (2002-04-01), Knudsen
patent: 6404372 (2002-06-01), Heithoff
patent: 6717945 (2004-04-01), Jue et al.
patent: 6744432 (2004-06-01), Morein
patent: 6816101 (2004-11-01), Hietala et al.
patent: 7262724 (2007-08-01), Hughes et al.
patent: 7333580 (2008-02-01), Parhi
patent: 2002/0186776 (2002-12-01), Cosand
patent: 2008/0048896 (2008-02-01), Parthasarthy et al.
Mangelsdorf, C.W., “A 400-MHz input flash converter with error correction”, IEEE Journal of Solid-State Circuits, pp. 184 - 191, Feb. 1990, vol. 25 Issue: 1.
Katsuria, S. et. al., “Techniques for High-Speed Implementation of Nonlinear Cancellation”, IEEE Joun. Communications, vol. 9, No. 5, Jun. 1991, pp. 711-717.
Chmelar Erik
Gribok Sergey
Ito Choshu
Loh William
Hamilton DeSanctis & Cha
Jean-Pierre Peguy
LSI Corporation
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