Electrical computers and digital processing systems: multicomput – Computer-to-computer direct memory accessing
Reexamination Certificate
1999-03-16
2001-10-30
Rinehart, Mark H. (Department: 2756)
Electrical computers and digital processing systems: multicomput
Computer-to-computer direct memory accessing
C709S250000, C370S392000, C370S397000, C370S399000, C370S409000, C711S108000, C365S049130
Reexamination Certificate
active
06311212
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to processing Virtual Connection Descriptors in networking systems, and more particularly to on-chip storage of Virtual Connection Descriptors on a single-chip network processing device to enhance system performance.
The need for faster communication among computers and other systems requires ever faster and more efficient networks. Today, networks typically use an amalgam of various software and hardware to implement a variety of network functions and standards. Network devices such as client computer systems, servers, hubs, routers, switches, network backbones, etc., are each complex devices that require digital processing in hardware and software to facilitate network communication. Some tasks performed in a network device include translation between different network standards such as Ethernet and Asynchronous Transfer Mode (ATM), reformatting of data, traffic scheduling, routing of data cells, packets messages, etc. Depending on the particular protocol being implemented, some tasks may be performed at different points in the network.
In conventional networking systems that implement asynchronous Transfer Mode (ATM), data traffic is handled by a Virtual Channel, or Virtual Connection (VC). There are typically many VCs in each system and each VC has its own characteristics, such as packet type, packet size and protocols. Therefore, each VC requires its own descriptor that identifies the particular VC and its characteristics and requirements. In a typical system, the VC descriptors are stored in the system memory. In order to process data for a VC (whether for receiving or transmitting data for a particular VC), the system reads the associated VC descriptor from the system memory, and then processes and updates the VC descriptor. However, system memories typically have limited bandwidth and slow memory access times, so data transfer performance and network efficiency can be degraded when accessing and processing VC descriptors stored on system memory. This is especially the case when processing data for certain VCs, such as VCs for real-time video or voice, which require high bandwidth and fast memory access times for optimal performance. Accordingly, what is needed in the art are techniques for improving the ability of a network device to process VC descriptors quicker so as to provide increased throughput and enhanced network efficiency.
SUMMARY OF THE INVENTION
The present invention provides techniques for storing, or caching, VC descriptors on a network processor to enhance system performance. In particular, the techniques of the present invention significantly increase throughput and reduce the bandwidth needed in the system memory to fetch, process and update VC descriptors.
According to the invention, a network processor includes an on-chip cache memory that stores VC descriptors for fast retrieval. When a VC descriptor is to be retrieved, a processing engine sends a VC descriptor identifier to a content-addressable memory (CAM), which stores VC descriptor identifiers in association with addresses in the cache where associated VC descriptors are stored. If the desired VC descriptor is stored in the cache, the CAM returns the associated address to the processing engine and the processing engine retrieves the VC descriptor from the cache memory. If the VC descriptor is not stored in the cache, the CAM returns a miss signal to the processing engine, and the processing engine retrieves the VC descriptor from an off-chip memory. In this manner, VC descriptors associated with high bandwidth VCs are stored to the cache and retrieved much quicker from the cache than from the off-chip memory.
According to an aspect of the invention, a networking system device is provided for use in network communication applications. The device typically comprises a network processor and an external local memory for storing a first plurality of virtual connection descriptors (VCDs). The network processor typically includes a cache memory for storing a second plurality of VCDs, a processing engine, coupled to the local memory and to the cache memory, for processing VCDs, and a content-addressable memory (CAM), coupled to the processing engine, wherein the CAM stores cache addresses of the second plurality of VCDs stored in the cache memory. In typical operation, the processing engine sends a first VCD identifier associated with a first VCD to the CAM, wherein the CAM reads the first VCD identifier and responds to the processing engine with one of a hit signal indicating that the first VCD is stored in the cache memory and a miss signal indicating that the first VCD is not stored in the cache memory. The processing engine accesses the first VCD in the cache memory if the hit signal is received, and the processing engine accesses the first VCD in the external local memory if the miss signal is received.
According to another aspect of the invention, a method is provided for locating virtual connection descriptors (VCDs) in a networking device that includes a processor coupled to a first memory for storing a first plurality of VCDs. The processor typically has a processing engine, a second memory for storing a second plurality of VCDs, and a content-addressable memory (CAM) that stores addresses of the VCDs stored in the second memory. The method typically comprises the steps of sending a first identifier from the processing engine to the CAM, wherein the first identifier is associated with a first VCD; determining in the CAM whether the first VCD is stored in the second memory; and responding to the processing engine with one of a hit signal if the first VCD is stored in the second memory and a miss signal if the first VCD is not stored in the second memory.
According to yet another aspect of the invention, a network device is provided for use in network communication applications. The device is coupled to a local memory for storing a first plurality of virtual connection descriptors (VCDs). The device typically comprises a cache memory for storing a second plurality of VCDs; a processing engine, coupled to the local memory and to the cache memory, for processing VCDs; and a content-addressable memory (CAM), coupled to the processing engine, wherein the CAM stores cache addresses of the second plurality of VCDs stored in the cache memory. In typical operation, the processing engine sends a first VCD identifier associated with a first VCD to the CAM, wherein the CAM reads the first VCD identifier and responds to the processing engine with one of a hit signal indicating that the first VCD is stored in the cache memory and a miss signal indicating that the first VCD is not stored in the cache memory.
Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.
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Bleszynski Ryszard
Chong Simon
Huang Anguo Tony
Stelliga David A.
Trinh Man Dieu
Blakely & Sokoloff, Taylor & Zafman
Intel Corporation
Rinehart Mark H.
Vaughn, Jr. William C.
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