Systems and methods for implementing delay line circuitry

Details Systems and methods for implementing delay line circuitry Systems and methods for implementing delay line circuitry

2007-01-02

2007-01-02

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S270000

Reexamination Certificate

active

10922803

ABSTRACT:
Memory devices used to control delay line circuitry, and that may be implemented in one embodiment to provide a self-tuning delay line device using empirical calibration technique/s to achieve a desired signal delay. The memory control device may be implemented to store electrical characteristics of the delay line circuitry during testing to enable self-calibration of the delay line circuitry.

REFERENCES:
patent: 5703515 (1997-12-01), Toyama et al.
patent: 5963074 (1999-10-01), Arkin
patent: 6051999 (2000-04-01), To et al.
patent: 6092030 (2000-07-01), Lepejian et al.
patent: 6104223 (2000-08-01), Chapman et al.
patent: 6121810 (2000-09-01), Philpott
patent: 6127869 (2000-10-01), Hirasaka
patent: 6385101 (2002-05-01), Chang et al.
patent: 6426721 (2002-07-01), Obara
patent: 6621315 (2003-09-01), Heo et al.
patent: 2005/0168260 (2005-08-01), Tomerlin et al.
Search Report; PCT/US05/29369; Jun. 20, 2006; 11 pgs.

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