Electrical computers and digital processing systems: processing – Processing architecture
Reexamination Certificate
2007-11-06
2007-11-06
Sparks, Donald (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
C711S155000
Reexamination Certificate
active
11070060
ABSTRACT:
Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.
REFERENCES:
patent: 4198699 (1980-04-01), Caddell
patent: 5317745 (1994-05-01), Chan
patent: 5568445 (1996-10-01), Park et al.
patent: 5577238 (1996-11-01), Cuny et al.
patent: 5915104 (1999-06-01), Miller
patent: 6147926 (2000-11-01), Park
patent: 6360307 (2002-03-01), Raftery et al.
patent: 6397274 (2002-05-01), Miller
patent: 6434674 (2002-08-01), DeWilde et al.
patent: 6697371 (2004-02-01), Liang et al.
patent: 2002/0122386 (2002-09-01), Calvignac et al.
patent: 2002/0161967 (2002-10-01), Kirihata et al.
“IBM PowerNP network processor: Hardware, software, and applications”; J. R. Allen, Jr., et al.; Mar. 2003.
Kwasnik, R. F., “Minimization of Latency in Serial Memories,” IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, pp. 2389-2390.
Calvignac Jean Louis
Chang Chih-jen
Logan Joseph Franklin
Verplanken Fabrice Jean
Cockburn Joscelyn G.
Geib Benjamin P.
Schubert Osterrieder & Nickelson PLLC
Sparks Donald
LandOfFree
Systems and methods for implementing counters in a network... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods for implementing counters in a network..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for implementing counters in a network... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3810909