Systems and methods for high density multi-component modules

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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C257SE21511

Reexamination Certificate

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07727806

ABSTRACT:
A method for forming a device, comprising providing a first substrate carrying a first set of components disposed in a first encapsulating layer over the first set of components, providing a second substrate carrying a second set of components disposed in a second encapsulating layer over the second set of components, bonding the first and second substrates and functionally interconnecting at least one of the predefined components in the first set of components with at least one of the components in the second set of components.

REFERENCES:
patent: 5108825 (1992-04-01), Wojnarowski et al.
patent: 5111278 (1992-05-01), Eichelberger
patent: 5162260 (1992-11-01), Leibovitz et al.
patent: 5250843 (1993-10-01), Eichelberger
patent: 5298288 (1994-03-01), Curry, II et al.
patent: 5841193 (1998-11-01), Eichelberger
patent: 5866952 (1999-02-01), Wojnarowski et al.
patent: 6117704 (2000-09-01), Yamaguchi et al.
patent: 6203967 (2001-03-01), Westbrook et al.
patent: 6424545 (2002-07-01), Burton
patent: 6440641 (2002-08-01), Lykins et al.
patent: 6544638 (2003-04-01), Fischer et al.
patent: 6882034 (2005-04-01), Corisis et al.
patent: 2004/0070083 (2004-04-01), Su
patent: 2004/0145051 (2004-07-01), Klein et al.
patent: 2004/0174223 (2004-09-01), Achyut
patent: 2005/0112798 (2005-05-01), Bjorbell
Ziptronix, Inc. whitepaper. 3D Integration for Mixed Signal Applications. (2002).
Takahashi et al. Development of Advanced 3D Chip Stacking Technology with Ultra-Fine Interconnection. IEEE 2001 Electronic Components and Technology Conference.
Koyanagi, et al., “Neuromorphic Vision Chip Fabricated Using Three-Dimensional Integration Technology,” 2001 IEEE International Solid-State Circuits Conference (2001).
Singer et al. Cost Considerations for CSP Variations. Presented at Chip Scale International, May 1998.
Kohl et al., Low cost chip scale packaging and interconnect technology. Proceedings of the Surface Mount International Conference (1997).
3D System Integration. Whitepaper of the Fraunhofer Institut, (2003).
Gann, Keith D. Neo-Stacking Technology. HDI Magazine (Dec. 1999).
Warner, et al. Layer Transfer of FDSOI CMOS to 150mm InP Substrates for Mixed-Material Integration. (2006).
Suntharalingarn, et al. Megapixel CMOS Image Sensor Fabricated in Three-Dimensional Integrated Circuit Technology. 2005 IEEE International Solid-State Circuits Conference (2005).
Aull, et al. Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers. 2006 IEEE International Solid-State Circuits Conference (2006).
Warner, et al. An Investigation of Wafer-to-Wafer Alignment Tolerances for Three-Dimensional Integrated Circuit Fabrication. (2004).
Burns, et al. A Wafer-Scale 3-D Circuit Integration Technology. IEEE Transaction on Electron Devices. 53:10, 2507-16 (Oct. 2006).
Yarema, Ray. Fermilab Initiatives in 3D Integrated Circuits and SOI Design for HEP. ILC Vertex Workshop. (May 2006).
Huffman, Alan. 50 Micron Pitch Flip Chip Bumping Technology: Processes and Applications. IEEE Components, Packaging & Manufacturing Technology Society. (2006).
Souriau, Jean-Charles. Wafer Level Processing of 3D System-in-Package for RF and Data Applications. 2005 IEEE Electronic Components and Technology Conference (2005).
Ziptronix, Inc. Benefits of 3D Integration in Digital Imaging Applications. Ziptronix whitepaper (2002).
Amkor Technology data sheet. Wafer Level Packaging CSP (2005).
Fusaro, Jim. Packaging Solutions for Mobile Applications. Amkor Technology presentation to JEDEC/CES (2007).
Quddus, M. JEDEC and Memory Standardization, (2007).
Cooke, Jim. Low power Mobile DRAM and PSRAM for Mobile Applications. JEDEC Presentation to CES 2007.
Garrou, P. Wafer-Level 3-D Integration Moving Forward.Semiconductor International(Oct. 1, 2006).
Garrou, P. Integrated Passives . . . Are We There Yet?Semiconductor International(Oct. 1, 2005).
Vitkavage, S. Making the Business Case for 3D.Future Fab International, vol. 22. (Jan. 9, 2007).
Singer, Peter. 3-D Die Interconnect Forecast.Semiconductor International(Nov. 1, 2006).
Peters, Laura. Deep Silicon Etching Gets Ready for 3-D ICs.Semiconductor International(Sep. 1, 2006).
Töpper et al. The Wafer-Level Packaging Evolution.Semiconductor International(Oct. 1, 2004).
Keser, B. Redistributed Chip Packaging. Semiconductor Packaging, (2005).
Pogge, H. Bernhard. Realizing Effective SOCs: From planar 2D to viable 3D ICs, (2004).
LoPiccolo, P. Mapping progress in 3D IC integration. Solid State Technology (2007).

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