Data processing: measuring – calibrating – or testing – Calibration or correction system – Circuit tuning
Reexamination Certificate
2001-09-24
2004-01-20
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Calibration or correction system
Circuit tuning
C702S106000, C377S020000, C327S291000, C714S055000, C714S727000, C714S731000
Reexamination Certificate
active
06681192
ABSTRACT:
TECHNICAL FIELD
The present invention relates to timers for computing systems. More particularly, the present invention relates to fast timer calibration, using a first timer running at a known speed to calibrate a second timer running at an unknown speed.
BACKGROUND
A computer system includes many different clocks (clocks, timers, counters, etc.) that are used by various processes to coordinate execution of instructions by the computer system. For example, a typical personal computer system may contain several of the following: an 8254 motherboard timer, a CMOS (complementary metal-oxide semiconductor) real-time clock, a central processing unit (CPU) cycle or timestamp counter, CPU performance counters (
2
), an APCI (advanced programmable interrupt controller) timer, a system bus clock, a local APIC (application-layer protocol control information) timer, etc. Some of these clocks are driven off of different crystals and, therefore, will not be exactly synchronized with each other.
There are many existing clock calibration methods that use a known clock to measure another clock. However, a problem exists with the known methods in that the calibration must be performed over a relatively long period to get acceptable accuracy. This is because the longer a time period in which calibration measurements are taken, the more accurate the calibration will be.
In today's environment of faster processor speeds and more precise execution timing requirements, there is a need for a precise clock calibration method that can be performed in a relatively short time period.
Consider real-time scheduling for example, wherein a real-time scheduler uses performance counters to drive the scheduler. A typical scheduler is designed to run all non-blocking threads for the same amount of time. However, the threads may not require all the scheduled time to run. To increase performance, a real-time scheduler is designed to run threads for the time required by the thread, up to a maximum time allotted by the real-time scheduler. However, for a real-time scheduler to function efficiently, different clock provided by a system must be calibrated so that scheduled events can be assured of occurring when the real-time scheduler expects them to be.
A real-time scheduler normally runs threads for somewhere between 500 nanoseconds (ns) and 500 microseconds (usec). The scheduler is also designed to run threads for different lengths of time; each thread is scheduled to run a fraction of every millisecond. The fraction the thread is allotted is determined by the percentage CPU reserved for that thread.
Because a real-time scheduler schedules threads to run in sub-ms time periods, it requires an accurate estimate of the speed of the clock driving the performance counters that it uses to generate the interrupts that drive the schedule. In addition, it is advantageous that adequate calibration can be accomplished within a relatively short period of time to accommodate more sophisticated systems.
SUMMARY
Systems and methods for fast timer calibration are described, wherein a first clock of a known speed is used to calibrate a second clock of unknown speed. The calibration can be done in a relatively short period of time and the first clock can run at a slower speed than the second clock. As used herein, the terms timer, clock and counter are interchangeable and are used to define a crystal oscillator used to generate a periodic electronic pulse that is used to drive a counter that counts either single or multiple clock pulses. All of these clocks or counters can be read, and can therefore be related to each other.
In a real-time scheduling system, performance counters can be set up to count cycles just like a timestamp counter of a processor. By calibrating the clock speed driving both sets of counters (performance and timestamp) the performance counters can be set up to generate interrupts for desired lengths of time. The real-time scheduler uses the performance counters to generate interrupts with potentially very short times between interrupts.
In one implementation, a first clock is used to calibrate a second clock that operates at a higher frequency. Over a short period of time, a series of measurement pairs are taken, each measurement pair including a measurement from the first clock and a measurement from the second clock taken as close together as possible. The series of measurement pairs are then stored in memory.
For each of the measurement pairs for which it is possible, a partial lower bound is derived that indicates a minimum number of second clock cycles that occur during a first clock cycle. Similarly, for each of the measurement pairs for which it is possible, a partial upper bound is derived that indicates a maximum number of second clock cycles that occur during a first clock cycle.
From the partial lower bounds and partial upper bounds, a lower and upper bound for the series of measurement pairs is derived. This can be done in several ways, e.g., taking an average or median of the lower and upper bounds, or taking a minimum partial lower bound for the lower bound of the series and taking a maximum partial upper bound for the upper bound of the series.
Once a lower bound and an upper bound have been derived for the series of measurement pairs, the lower bound and upper bound are used to calculate a calibration variable that indicates the number of cycles that occur on the second clock during one cycle of the first clock. In one implementation, the calibration variable is derived by taking an average of the lower bound and the upper bound.
One advantage realized by the invention described herein is that it can calibrate a faster clock in relation to a slower clock in a relatively short period of time. For example, to take ten measurement pairs from a clock running at one megahertz, only ten microseconds are required.
In one example of one implementation, to quickly calibrate a CPU cycle counter, several measurements from a motherboard timer running at a known nominal speed of 1.193182 MHz can be taken in a short time period (approximately 10 msec). The measurements are used as described above to accurately estimate a clock speed of the CPU cycle counter
REFERENCES:
patent: 5502812 (1996-03-01), Leyre et al.
patent: 6169502 (2001-01-01), Johnson et al.
Barlow John
Lee & Hayes PLLC
Microsoft Corporation
Vo Hien
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