Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2000-11-28
2003-06-10
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C716S030000
Reexamination Certificate
active
06577980
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits and, in particular, to systems and methods for facilitating, within an integrated circuit, receiver trip level testing of pads of the integrated circuit.
2. Description of the Related Art
Heretofore, integrated circuit (IC) devices have been tested and verified using a variety of test methods. For example, IC devices have been tested and verified to be defect-free using functional test vectors, such as those applied to the IC by the use of automated test equipment (ATE), which stimulate and verify the IC device functionality at the pin level of the device. A practical limitation to the utilization of ATE for testing IC's, however, is that the number of IC pins (or pads) that can be tested by a particular ATE has, heretofore, been limited by the physical configuration of the ATE. For instance, the number of pads of the IC to be tested may exceed the number of test channels provided by an ATE, or the number of pads may exceed the capacity of the ATE support hardware, such as by exceeding the maximum number of probes on a probe card, among others. As utilized herein, the term “pad” is used to refer collectively to both a physical site, which serves as an electrical contact for an IC, as well as circuitry associated with the physical site for enabling electrical communication between components of the IC and components external to the IC.
Additionally, performance limitations of a particular ATE may impose certain other testing restrictions. For example, the frequency of IC inputs and outputs may exceed the maximum frequency of the ATE, thereby limiting the test frequency of the IC to be tested to the maximum frequency of the ATE. Although configuring an ATE with additional test channels and/or a higher operating frequency may be accomplished, providing an ATE with an appropriately high pin count and/or an appropriately high operating frequency in order to eliminate the aforementioned deficiencies is, oftentimes, cost prohibitive.
In light of the foregoing and other deficiencies, it is known in the prior art to test IC devices utilizing a variety of “stop-gap” testing procedures, including: (1) connecting an ATE to less than all of the pins of an IC device; (2) connecting multiple pins of an IC device to a single ATE test channel; (3) testing the IC device in multiple passes of the ATE, with each pass testing a subset of the pins of the entire IC device; (4) testing the device at less than maximum frequency, and; (5) limiting, through design implementation, the pin count and/or frequency of the IC device to accommodate existing ATE, among others. As should be readily apparent, many of these “stop-gap” testing procedures may result in a loss of test coverage and, thereby, may lead to an increase in numbers of defective IC devices being shipped. Moreover, the practice of limiting, through design implementation, the pin count and/or frequency of the IC device to accommodate existing ATE is, oftentimes, an unacceptable constraint on IC design.
Therefore, there is a need for improved systems and methods which address these and other shortcomings of the prior art.
SUMMARY OF THE INVENTION
Briefly described, the present invention provides receiver trip level testing functionality within integrated circuits. In this regard, some embodiments of the present invention may be construed as providing integrated circuits (IC's). In a preferred embodiment, the integrated circuit includes a first pad incorporating a first driver and a first receiver. The first driver is configured to provide a first pad output signal to a component external to the IC. The first receiver is configured to receive a first pad input signal from a component external to the IC, and to provide a first receiver digital output signal to a component internal to the IC in response to the first pad input signal. Additionally, a first test circuit is provided that is arranged internal to the IC, with the first test circuit being adapted to provide information corresponding to at least one receiver trip-level characteristic of the first receiver of the first pad.
In an alternative embodiment, the integrated circuit includes a first pad incorporating a first driver and a first receiver, and means for providing information corresponding to at least one receiver trip-level characteristic of the first receiver of the first pad.
Some embodiments of the present invention may be construed as providing systems for measuring receiver trip-level characteristics. In this regard, a preferred embodiment includes automated test equipment (ATE) and an integrated circuit (IC). Preferably, the ATE is configured to electrically interconnect with the IC and to provide at least one stimulus to the IC. The IC includes a first pad that incorporates a first driver, a first receiver and a first test circuit. The first driver is configured to provide a first pad output signal to the ATE. The first receiver is configured to receive a first pad input signal from the ATE and to provide a first receiver digital output signal to a component internal to the IC in response to the first pad input signal. Additionally, the first test circuit is configured to electrically communicate with the ATE so that, in response to receiving at least one stimulus from the ATE, the first test circuit provides information to the ATE corresponding to at least one receiver trip-level characteristic of the first receiver of the first pad.
Some embodiments of the present invention may be construed as providing methods for testing an integrated circuit. In this regard, a preferred method includes the steps of: electrically interconnecting ATE with the IC; providing at least one stimulus from the ATE to the IC so that the IC measures a receiver trip-level characteristic of the first pad of the IC; and receiving information corresponding to a receiver trip-level characteristic of the first pad.
Other embodiments of the present invention may be construed as providing computer readable media. In this regard, a preferred computer readable medium, which incorporates a computer program for facilitating measuring of a receiver trip-level characteristic of an IC, includes: logic configured to enable ATE to provide at least one stimulus to the IC so that a first test circuit provides information corresponding to at least one receiver trip-level characteristic of a first receiver of the IC; and logic configured to enable the ATE to receive, from the first test circuit, the information corresponding to the at least one receiver trip-level characteristic of the first receiver.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such features and advantages be included herein within the scope of the present invention, as defined in the appended claims.
REFERENCES:
patent: 5977775 (1999-11-01), Chandier et al.
patent: 6275962 (2001-08-01), Fuller et al.
patent: 6324485 (2001-11-01), Ellis
patent: 6396279 (2002-05-01), Gruenert
Rearick Jeffrey R.
Rohrbaugh John G.
Shepston Shad R.
Agilent Technologie,s Inc.
Hoff Marc S.
Raymond Edward
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