Amplifiers – With periodic switching input-output
Reexamination Certificate
2000-07-18
2002-03-12
Pascal, Robert (Department: 2817)
Amplifiers
With periodic switching input-output
C327S124000
Reexamination Certificate
active
06356148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to systems and methods for amplifying electrical signals. More specifically, the present invention relates to systems and methods for enhancing charge transfer amplifier gain.
2. The Prior State of the Art
There are many circuits and methods conventionally available for amplifying an electrical signal. One type of amplifier is called a charge transfer amplifier. Charge transfer amplifiers operate on the principle of capacitive charge sharing. Voltage amplification is achieved by transferring a specific amount of charge between appropriately sized capacitors through an active device.
FIG. 1
illustrates a charge transfer amplifier
100
that utilizes an nMOS transistor N
1
to transfer charge between capacitors CT and CO. The operation of the nMOS charge transfer amplifier
100
will now be described in order to illustrate the basic principle of charge transfer amplification.
The nMOS charge transfer amplifier
100
operates in a cycle of three phases including a reset phase, a precharge phase, and an amplify phase.
FIG. 2
is a signal timing diagram for two input signals S
1
and S
2
with respect to the cycle phase that the nMOS charge transfer amplifier
100
is operating in whether that phase be (a) the reset phase, (b) the precharge phase or (c) the amplify phase. The two input signals S
1
and S
2
control corresponding switches S
1
and S
2
of FIG.
1
. Switch !S
1
corresponds to the inverse phase of the input signal S
1
.
The cycle begins with the (a) reset phase in which both input signals signal S
1
and S
2
are high indicating that switches S
1
and S
2
are closed and that switch !S
1
is open. Since the switch S
1
is closed, the upper terminal of capacitor CT (i.e., node A) is discharged through the switch S
1
to voltage Vss. Since the switch S
2
is closed, the upper terminal of capacitor CO (i.e., node B is charged to a voltage V
PR
. The open switch !S
1
prevents static current from flowing through the nMOS transistor N
1
.
After the reset phase is the (b) precharge phase in which the signal S
1
is low indicating that switch S
1
is open and the switch !S
1
is closed, and in which the signal S
2
is high indicating that the switch S
2
remains closed. Thus, the upper terminal of the capacitor CO (i.e., node B) remains charged at the precharge voltage V
PR
. This precharge voltage V
PR
is high enough that current flows from node B to the capacitor CT (and node A) through the nMOS transistor N
1
and the switch !S
1
. For example, if the precharge voltage V
PR
is at least equal to the input voltage V
IN
at the gate of the nMOS transistor N
1
, then the discharge continues until the voltage at the capacitor CT increases to be equal to the input voltage V
IN
minus the threshold voltage (hereinafter “V
TN
”) of the nMOS transistor N
1
. At that point, the nMOS transistor N
1
enters the cutoff region and current flow to the capacitor C
T
substantially ceases. Thus, at the end of the precharge phase, the capacitor CO ideally has a voltage of V
PR
while the capacitor CT has a voltage of V
IN
-V
TN
.
After the precharge phase is the (c) amplify phase in which both signals S
1
and S
2
are low indicating that both switches S
1
and S
2
are open. During the amplify phase, an incrementally positive input voltage change &Dgr;V
IN
at the gate of the nMOS transistor N
1
will cause the nMOS transistor N
1
to turn on thereby allowing current to flow through the nMOS transistor N
1
until the nMOS transistor is again cutoff. For small incrementally positive voltage changes &Dgr;V
IN
, the nMOS transistor N
1
will cutoff when the voltage on the upper terminal of the capacitor CT (i.e., node A) increases by the incrementally positive voltage change &Dgr;V
IN
. The amount of charge transferred to the capacitor CT in order to produce this effect is equal to the incrementally positive voltage change &Dgr;V
IN
times the capacitance C
T
of the capacitor CT.
Since the charge &Dgr;V
IN
×C
T
transferred to the capacitor CT came from node B through transistor N
1
, the charge &Dgr;V
IN
×C
T
was drawn from the capacitor CO. Thus, the voltage at the capacitor CO and the output voltage V
OUT
will change by &Dgr;V
IN
×(C
T
/C
0
). If the capacitance C
T
is greater than the capacitance C
0
, amplification occurs.
One advantage of the nMOS charge transfer amplifier
100
is that the voltage gain and power consumption maybe controlled by setting the capacitance of the capacitors CO and CT as well as by setting the capacitance ratio C
T
/C
0
. Another advantage of charge transfer amplifiers in general is that the circuit performance is generally unaffected by the absolute values of the supply voltage Vss and Vdd as long as these voltages permit proper biasing during the reset and precharge phases. In other words, charge transfer amplifiers have high supply voltage scalability in that no changes are needed for a charge transfer amplifier to operate using a wide range of supply voltages Vss and Vdd.
Although the nMOS charge transfer amplifier
100
has these advantages, amplification only occurs in the nMOS charge transfer amplifier
100
if the input gate voltage change &Dgr;V
IN
is positive. A negative gate voltage change &Dgr;V
IN
would only cause the nMOS transistor N
1
to enter deeper into the cutoff region. Thus, charge transfer between node A and node B would be stifled thereby preventing amplification.
FIG. 3
shows a conventional CMOS charge transfer amplifier
300
that amplifies using positive input voltage changes &Dgr;V
IN
as well as negative input voltage changes &Dgr;V
IN
. The CMOS charge transfer amplifier
300
includes the nMOS charge transfer amplifier
100
described above. For clarity, the nMOS charge transfer amplifier
100
is shown in
FIG. 3
as being enclosed by a dotted box.
The CMOS charge transfer amplifier
300
also includes a partially overlapping pMOS charge transfer amplifier
301
which is shown in
FIG. 3
enclosed by a dashed box for clarity. The pMOS charge transfer amplifier
301
shares the voltage input line
302
, the voltage output line
303
and the precharge line
304
with the nMOS charge transfer amplifier
100
. The pMOS charge transfer amplifier
301
is structured similar to the nMOS charge transfer amplifier
100
except that the pMOS charge transfer amplifier
301
uses a pMOS transistor P
1
instead of an nMOS transistor N
1
for transferring charge between capacitors. Also, node A′ of the pMOS charge transfer amplifier
301
is reset to a high voltage Vdd instead of the low voltage Vss and is capacitively coupled to the high voltage Vdd instead of the low voltage Vss.
The general operation of the pMOS charge transfer amplifier
301
for negative input voltage changes &Dgr;V
IN
is similar to the operation of the nMOS charge transfer amplifier
100
for positive voltage changes &Dgr;V
IN
Thus, the input signals S
1
and S
2
of
FIG. 2
are used in the operation of the CMOS charge transfer amplifier
300
. Due to the complementary nature of the nMOS charge transfer amplifier
100
and the pMOS charge transfer amplifier
301
, the CMOS charge transfer amplifier
300
amplifies for both positive and negative input voltage changes &Dgr;V
IN
.
The CMOS charge transfer amplifier
300
is advantageous in that it consumes no static current, capitalizes on parasitic capacitors, is memory less, operates over a wide voltage supply range, produces little noise, is insensitive to threshold voltage fluctuations, and comprises relatively few devices. However, it would represent an advancement in the art to create a system and method in which the gain of the charge transfer amplifier is enhanced without giving up any of the advantages inherent in the charge transfer amplifier.
SUMMARY AND OBJECTS OF THE INVENTION
The foregoing problems in the prior state of the art have been successfully overcome by the present invention, which is directed to an enhanced gain amplifier for use with charge tran
AMI Semiconductor Inc.
Choe Henry
Pascal Robert
LandOfFree
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