Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2007-08-14
2007-08-14
Shah, Kamini (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C703S015000, C703S016000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11059265
ABSTRACT:
A method for simulating a circuit includes representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph. The method further includes arranging the subcircuits from the hierarchically arranged set of branches into one or more groups, determining a data structure for each subcircuit in a group that supports a combination of selectively flattened and selectively expanded group of subcircuits, selecting a subcircuit as a simulation leader and identifying remaining subcircuits as followers in the group, where the simulation leader have states substantially equivalent to the followers, simulating the respective simulation leader of each group using a selectable simulation driver, and replicating simulation results of the respective simulation leader of each group to its followers.
REFERENCES:
patent: 6134513 (2000-10-01), Gopal
patent: 6148433 (2000-11-01), Chowdhary et al.
patent: 6381563 (2002-04-01), O'Riordan et al.
patent: 6577992 (2003-06-01), Tcherniaev et al.
patent: 7143021 (2006-11-01), McGaughy et al.
patent: 2003/0163297 (2003-08-01), Khaira et al.
patent: 2005/0143966 (2005-06-01), McGaughy
patent: 2005/0149311 (2005-07-01), McGaughy
Beatty, D. et al. (1988). “Fast Incremental Circuit Analysis Using Extracted Hierarchy,”25thACM/IEEE Design Automation Conference, Paper 33.1, pp.495-500.
Jiang, X. et al. (1999). “Optimal quadratio-time isomorphism of ordered graphs,”Pattern Recognition, 32:1273-1283.
Kevenaar, T. et al. (1991). “A Flexible Hierarchical Piecewise Linear Simulator,” INTEGRATION,the VLSI Journal, 12:211-235.
Saviz, P. et al. (Jun. 1993), “Circuit Simulation by Hierarchical Waveform Relaxation,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(6):845-860.
Saviz, P. et al. (1988). “PYRAMID—A Hierarchical Waveform Relaxation-Based Circuit Simulation Program,”IEEE, pp.442-445.
Pillage, L.T. et al. (1995). “Linear dc Nodal Analysis,” Chapter 2In Electronic Circuit and System Simulation Methods. McGraw-Hill, Inc.: New York, NY, pp. 27-45.
Pillage, L.T. et al. (1995). “Simulation of Nonlinear Circuits,” Chapter 10In Electronic Circuit and System Simulation Methods. McGraw-Hill, Inc.: New York, NY, pp. 285-314.
Saleh, R.A. et al. (1990). “Electrical Simulation Techniques,” Chapter 2In Mixed-Mode Simulation. Kluwer Academic Publishers: Norwell, MA, pp. 19-44.
Cadence Design Systems Inc.
Day Herng-der
Morrison & Foerster / LLP
Shah Kamini
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