Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-11-28
2006-11-28
Ferris, Fred (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C703S014000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07143021
ABSTRACT:
A machine-implemented, simulations-supporting system creates a hierarchy of data structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso-static instances of subcircuit-definitions. The behaviors of such isomorphic and iso-static instances can be simultaneously predicted by appointing a simulation leader for them and using the simulation leader in combination with a respective simulation model to predict the behavior of the simulation leader. The predicted behavior of the leader is then copied for the followers. In one embodiment, state-describing S-circuit cards each point to a respective, and possibly merged, I-circuit card. The I-circuit cards each point to respective, and possibly merged, element instantiating cards (AG-cards) as well as to respective, and possibly merged, interconnect-topology describing cards (T-circuits). If the handles (SH's) of two or more subcircuit parts point to a same, state-describing S-part, where the latter points to a merged I-circuit, and where the latter points to a merged T-circuit, then it can be determined by this that the respective subcircuit parts are both isomorphic and substantially iso-static and can therefore follow a commonly appointed leader. The disclosed system can be used with fully-flattened design definitions as well as with highly hierarchical design definitions.
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Karhade Prashant
McGaughy Bruce W.
Singh Manish
Wan Peng
Cadence Design Systems Inc.
Ferris Fred
Morrison & Foerster / LLP
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