Systems and methods for control flow error detection in reduced

Details Systems and methods for control flow error detection in reduced Systems and methods for control flow error detection in reduced

1998-05-12

1999-10-26

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

714758, 714 45, 714 51, 712239, G06F 938, G06F 939, G06F 1114

Patent

active

059745290

ABSTRACT:
An instruction flow monitoring mechanism performs control flow error detection in a reduced instruction set computer (RISC) processor using signature monitoring. The signature monitoring is integrated into the RISC processor such that the instruction set of the RISC processor is enhanced to perform signature checking under all execution conditions. A signature monitor instruction causes the instruction flow to be checked for errors by comparing a pre-computed reference signature with a current signature and raising an error condition if the two signatures are unequal. The instruction also initializes the current signature.

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patent: 5630056 (1997-05-01), Horvath et al.
patent: 5742851 (1998-04-01), Sekine
patent: 5812761 (1998-09-01), Seki
patent: 5829031 (1998-10-01), Lynch

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