Systems and method for a delay locked loop with false-lock...

Details Systems and method for a delay locked loop with false-lock... Systems and method for a delay locked loop with false-lock...

2007-11-27

2007-11-27

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000

Reexamination Certificate

active

11194085

ABSTRACT:
A DLL comprises detection circuitry configured to detect a too_slow and a too_fast operating state and correction circuitry configured to correct operation of the DLL when a too_fast or too_slow state is detected. The correction circuitry can be configured to swallow a pulse of the input clock signal when a too_fast condition is detected. The correction circuitry can also be configured to force the DLL into a too_fast operation state, when a too_slow operation state is detected. The correction circuitry can then also be configured to swallow a pulse of the input clock signal once the DLL is in the too_fast operation state.

REFERENCES:
patent: 5889436 (1999-03-01), Yeung et al.
patent: 6140880 (2000-10-01), Moyal et al.
patent: 6803797 (2004-10-01), Park
patent: 2006/0132205 (2006-06-01), Wu et al.
patent: WO 2005027349 (2005-03-01), None

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