Static information storage and retrieval – Interconnection arrangements
Patent
1996-10-10
2000-09-05
Nelms, David
Static information storage and retrieval
Interconnection arrangements
365 72, 365148, 365 51, G11C 506
Patent
active
06115279&
ABSTRACT:
A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
REFERENCES:
patent: 4975874 (1990-12-01), Childers et al.
patent: 5388068 (1995-02-01), Ghoshal et al.
patent: 5650972 (1997-07-01), Tomishima et al.
Sugibayashi et al., A 30-ns 256 Mb DRAM with a Multidivided Array Structure, Nov. 1993, pp. 1092-1098.
Yamada et al., A 64-Mb DRAM with Meshed Power Line, Nov. 1991, pp. 1506-1510.
Noda et al., A Boosted Dual Word-Line Decoding Scheme for 256Mb DRAMs, pp. 112-113.
Akiba Takesada
Herndon Troy H.
Kitsukawa Goro
Koelling Jeffrey E.
McKee William R.
Hitachi , Ltd.
Nelms David
Tran Andrew Q.
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