Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-06-21
2011-06-21
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050
Reexamination Certificate
active
07965581
ABSTRACT:
According to the system of the present invention, data (DQ) signals are outputted/received between a controller100and a memory200based on a data strobe signal sent out from the controller100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory200is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
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Elpida Memory Inc.
Sughrue & Mion, PLLC
Tran Michael T
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