System with chrominance delay lines

Details System with chrominance delay lines System with chrominance delay lines

1999-05-21

2002-12-17

Miller, John (Department: 2711)

Television

Image signal processing circuitry specific to television

Chrominance signal demodulator

C348S639000, C348S664000, C348S666000, C348S713000

Reexamination Certificate

active

06496227

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of television, and, more particularly, to demodulation of chrominance signals.
BACKGROUND OF THE INVENTION
Demodulation of chrominance signals in the PAL or SECAM television standard involves the use of delay lines, which typically provides a 64 &mgr;s delay. In the PAL standard, the purpose of the delay line is to compensate for phase errors between U and V chrominance signals. In the SECAM standard, the purpose of the delay line is to restore the continuity of signals between successive lines. Traditionally, this type of delay line, which may be a line with piezo-acoustic delay, is inserted as a sub-carrier before demodulation. However, in integrated manufacturing, this delay line usually operates in baseband and is inserted after demodulation.
FIG. 1
schematically illustrates a chrominance demodulator with a delay line operating in baseband, according to the prior art.
FIG. 1
corresponds to
FIG. 1
disclosed in an article by Van Gurp et al., titled “Switched Capacitor Chrominance Base-Band Delay Lines For Colour Decoders.” This article is in the IEEE Transactions On Consumer Electronics, volume CE-33, number 3, Aug. 1987, and describes a circuit with switched capacitor baseband delay lines used for chrominance decoders.
The system illustrated in
FIG. 1
includes a passband filter
10
which receives the composite video broadcasting signal (CVBS), and outputs the modulated chrominance signal CH. It is followed by the chrominance decoder
11
. The chrominance decoder
11
has two outputs R-Y and B-Y, which are connected to respective delay lines
12
and
13
with a 64 &mgr;s delay or line duration. The input and output from each of these delay lines
12
,
13
are connected to two inputs of a respective adder
14
and
15
. A delay line thus combined with an adder forms a comb filter. The upper limits for this type of filter are integer multiples of the line frequency, and the lower limits are half-multiples of the line frequency.
The delay line circuit illustrated in
FIG. 1
operates as a comb filter and line memory for the PAL and SECAM standards, and may be formed in an integrated circuit. As described in the above referenced article by Van Gurp et al., each delay line may be a switched capacitor delay line. Such a line is made by multiple sampling, and is sequenced by a clock servo-controlled to the line frequency. The use of a sampled system then requires continuous filtering before (pre-filtering) and after sampling. Pre-filtering (or anti-backflow filtering) is not shown in FIG.
1
. In this circuit, the signal to be delayed is then sampled and then delayed by about one line duration in the delay line. A continuous filter then eliminates clock residues. The addition of a signal delayed by one line duration at the unsampled input signal produces the comb filter function.
The circuit in
FIG. 1
has the following advantages. In the PAL standard, it reduces interference between the different color signals. In the SECAM standard, it reduces diaphoty. Diaphoty is the interference between chrominance sub-carrier signals in the absence of color, which causes ripple patterns. In the NTSC standard, the circuit rejects luminance residues. Therefore, this type of circuit is compatible with all standards.
An, article titled “A Full Integrated Automatic Multistandard Chroma Decoder,” by Imbert et al., found in the IEEE Transactions On Consumer Electronics, volume 37, number 3, Aug. 1991, describes a multi-standard automatic and integrated chrominance decoder using a BICMOS process combining bi-polar and CMOS circuits. The article also describes a chrominance-baseband delay line including a series of 192 capacitors that are switched one after the other by a sequential pulse generator. These 192 capacitors are switched sequentially by a 192-stage offset register to a write line, and then 64 &mgr;s later to a read line. These lines are synchronized by a phase locking loop (PLL) at 6 MHz servo-controlled on the line frequency.
Therefore, as illustrated in
FIG. 2
, the prior art includes a technique of placing an analog low-pass filter
20
having an order of 2 to 4 on the output side of the delay line
12
. The delay introduced by this filter
20
must then be used in the total delay created by the delay line
12
. This type of manufacturing is described in the article by Van Gurp et al.
Since the delay due to the delay line
12
itself is related to the clock frequency, specifications for this filter
20
must include frequency and time parameters. These constraints make the design difficult and limitations may be necessary. The most serious of these limitations concerns the differential pulse response. Since the same filtering is not applied to the direct channel (without a delay line), pulse responses of the direct channel and the delayed channel are different. Since the transition times (rise time and fall time) of the direct channel are better than those of the delayed channel, the image suffers from a visible line by line degradation, especially in SECAM. The line degradation is a red-blue indentation called either an FL/
2
effect, a line frequency/
2
effect, or a mouse tooth effect.
SUMMARY OF THE INVENTION
An object of the invention is to overcome the above described disadvantages by providing a system in which the response of direct and delayed channels is balanced.
This invention relates to a system with chrominance delay lines having a first sampled channel including at least one smoothing filter, and having a second unsampled channel. The system includes a continuous compensation low-pass filter in the second channel to balance the pulse response of these two channels.
In a first approach, a system with chrominance delay lines includes a first delay line and a second delay line for receiving the chrominance demodulator output signals. The outputs from the first and second delay lines are respectively connected to a first input of a first and a second adder through a first smoothing by-pass filter. The inputs of the first and second delay lines are respectively connected to a second input of the first and the second adders through a second continuous compensation low-pass filter. This second filter balances the pulse response.
In a second embodiment, the system includes a third filter placed between the output from the delay line and the first input of the corresponding adder, and a fourth low-pass filter is placed at the adder output for each delay line. The third filter is advantageously a wideband filter capable of compensating the excess delay created by the first filter in the direct channel without modifying the frequency response. The fourth filter provides complementary rejection of the sampling and sub-carrier residues.
The invention also relates to an integrated television processing circuit including the system described above.


REFERENCES:
patent: 3553353 (1971-01-01), Melchior
patent: 3663746 (1972-05-01), Backers et al.
patent: 4064531 (1977-12-01), Koubek
patent: 4081827 (1978-03-01), Hipwell
patent: 4271427 (1981-06-01), Van Den Driessche
patent: 4409612 (1983-10-01), Warmuth
patent: 4605950 (1986-08-01), Goldberg et al.
patent: 5047841 (1991-09-01), Robinson
patent: 5194938 (1993-03-01), Imbert et al.
patent: 5374962 (1994-12-01), Klink
patent: 5459524 (1995-10-01), Cooper
patent: 5808701 (1998-09-01), Lee
patent: 6038276 (2000-03-01), Dinh
patent: 6323913 (2001-11-01), Prange
8087 IEEE Transactions on Consumer Electronics, Gurp et al., Switched Capacitor Chrominance Base Band Delay Lines for Colour Decoders, Aug. 1987, No. 3, New York, NY, USA, pp. 451-454.

Affiliated with

Also associated with

Rating

System with chrominance delay lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System with chrominance delay lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System with chrominance delay lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2989314