System with adjustable ADC clock phase

Details System with adjustable ADC clock phase System with adjustable ADC clock phase

1999-06-04

2001-10-30

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

Reexamination Certificate

active

06310570

ABSTRACT:

This invention relates to clocking analog to digital converters and more particularly phasing the clock signal to an analog to digital converter on an IC having a multiplicity of different clock signals.
BACKGROUND OF THE INVENTION
Digital processing integrated circuits (DSP's) containing a plurality of analog to digital converters (ADC's) are becoming prevalent. Frequently the DSP's will have a plurality of functional elements, with respective elements clocked at different frequencies, though the ADC's may be clocked at the same frequency. The relative proximity of respective ADC's to various of the functional elements may adversely affect the performance of the ADC. It is known that coupling of clocking signals from the functional elements or clock buses to the ADC either through the silicon substrate or via radiation will tend to degrade ADC performance, particularly if the ADC is operating near its maximum conversion rate.
Examples of DSP's containing a multiplicity of ADC's are multistandard interface circuits which condition signals in differing formats for processing by a common circuit element. A particular example is a television signal interface which conditions signal from different sources for digital processing and display. This interface may simultaneously accept NTSC signals from a broadcast receiver tuner, component analog television signals from a satellite or cable box, digitally broadcast VSB (vestigial sideband) signal from a further tuner etc. Nominally all of the signals will be converted from analog to digital form at a common sample rate and applied to respective processing elements for application to a display circuit. In the case of the digital VSB signal the processing will include digital decompression.
Depending on the format of the respective signals, different signal processing will be performed on the respective converted signal. The various processing functions may be performed at different clocking rates. Typically the ADC used to convert a signal of a particular format will be located in proximity of the processing element to which the converted signals applied. Depending on the clock frequencies utilized in the processing element and the relative nearness of the processing element to the ADC, ADC performance will be more or less affected.
In general the different clocking signals induce electrical noise in ADC conversion process, which in turn affects conversion speed, accuracy, and linearity. It is important to reduce the effects of clock signal or digitally induced noise on the analog or analog to digital circuitry.
In mixed analog-digital integrated circuitry it is known to take preventative measures to minimize effects of digital interference due to clock coupling. These measures include fabricating isolation guard rings around respective processing elements, and providing separate power buses to the different processing elements. Another technique includes the use of differential processing elements which may be arranged to reduce undesirable common mode signal.
SUMMARY OF THE INVENTION
Performance of respective ADC's on circuitry containing a plurality of processing elements, and a plurality of associated clock signals of differing frequencies is enhanced by generating ADC clocking signals of varying phase and selecting an optimum one of the clock phases for application to the ADC.


REFERENCES:
patent: 6005507 (1999-12-01), Nakatsu et al.

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