System utilizing multiple address decode resources and decoder r

Details System utilizing multiple address decode resources and decoder r System utilizing multiple address decode resources and decoder r

1995-10-19

1997-09-16

Lee, Thomas C.

395299, 395831, 39520059, G06F 1210, G06F 1312

Patent

active

056689497

ABSTRACT:
A hybrid decoding module which resides on the computer system's high speed memory bus. The computer system incorporating the hybrid decoding module scheme is capable of having centrally decoded resources on the memory bus as well as resources capable of decoding memory bus addresses directly. During system initialization, or after a hard reset, the decoding logic polls each of the resources on the memory bus to determine whether the resource is a centrally decoded resource or a distributed decode resource. A table is maintained for all centrally decoded resources such that when addresses are put out by the processor during run-time, the decoding logic is capable of directing control to the centrally decoded resource. Another aspect of the present invention is implemented during the initialization of the system. When resources are polled by the decoding logic, they are also provided with an identifier which identifies the last available I/O space slot. If the memory bus resource requires this I/O space for its own use, it signals the decoding module that it should be assigned to that resource.

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Intel DataBook 1991 - Microprocessors vol. II, (Intel Corporation, 1991). pp. 5-171-5-247.

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