System to reduce unwanted oscillations in high speed, high...

Amplifiers – With semiconductor amplifying device – Including atomic particle or radiant energy impinging on a...

Reexamination Certificate

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C250S2140AG, C330S297000

Reexamination Certificate

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06952136

ABSTRACT:
A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

REFERENCES:
patent: 6249621 (2001-06-01), Sargent, IV et al.
patent: 6492872 (2002-12-01), Fujioka et al.
patent: 6566954 (2003-05-01), Miyazawa
patent: 6639473 (2003-10-01), Kobayashi
patent: 6856201 (2005-02-01), Gupta
patent: 0 525 807 A2 (1993-02-01), None
Yoon, T. and Jalali, B., “Front-End CMOS Chipset for Fiber-Based Gigabit Ethernet,”Symposium on VLSI Circuits Digest of Technical Papers, IEEE, 1998, pp. 188-191.
Lee, W.S. et al., “Monolithic Integration of an InP/InGaAs Four-Channel Transimpedance Optical Receiver Array,”Electronic Letters, IEE, vol. 26, No. 22, Oct. 25, 1990, pp. 1833-1834.
Copy of European Search Report for Appln. No. EP 03 01 9369, mailed Dec. 11, 2003, 3 pages.

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