Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2000-02-11
2002-04-23
Zimmerman, Mark (Department: 2671)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S028000, C712S023000, C712S034000, C711S209000
Reexamination Certificate
active
06378060
ABSTRACT:
REFERENCES TO APPENDICES
All narrative material in the appendices as filed on Feb. 11, 2000, were incorporated into the specification on pages 31-68 of the specification. All graphical illustrations in the appendices as filed on Feb. 11, 2000, were incorporated into the drawings in
FIGS. 8
,
9
,
10
A,
10
B,
10
C,
10
D,
10
E,
11
A,
11
B,
11
C,
11
D,
12
A,
12
B,
12
C,
13
,
14
,
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16
A,
16
B,
16
C,
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FIELD OF THE INVENTION
The present invention relates to cross-bar circuits, and particularly relates to a cross-bar circuit implementing a switch of a broadband processor.
BACKGROUND AND SUMMARY OF THE INVENTION
In digital processing systems, one of the basic operations is rearranging or copying portions of an operand. Prior art systems, such as current general purpose microprocessors (Pentium, MIPS, ARM, SPARC, PowerPC, etc.), implement this basic operation in various special circuits, such as shifters, rotators, field extractors, or byte permuters.
Digital processing is now being extended to new applications such as broadband processing in which very general rearrangements of bits are required to accomplish various sophisticated mathematical algorithms needed for encryption and error correction. Such digital processing requires switching circuits, cross-bar circuits, to help accomplish these algorithms. General switching requires a cross-bar circuit, which conventionally contains more transistors than the specialized shifters, rotator, etc. used in the prior art.
Prior art cross-bar circuits require far more bits of control to specify the mapping between the location of output operand bits and the input operand bits from which they are generated.
The present invention provides a cross-bar circuit that implements a switch of a broadband processor. The present invention describes a system and method for implementing switching operations that perform completely general permutations and copies at the individual bit level within large operands.
The present invention describes a system and method for reducing the transistor count, wire count, and area of a general cross-bar network down to levels comparable to what is achieved in more specialized circuits. This invention involves a novel combination of circuit techniques, including precharged dynamic multiplexors, ground selection, and pseudo-differential sensing against dummy bit lines, which have individually been practiced in digital logic and memory devices.
The present invention implements the system and method for utilizing wide operands further described in commonly-assigned U.S. patent application Ser. No. 09/382,402 to provide these control bits from a small cache memory physically located close to the cross-bar circuit.
The present invention also describes a system and method for utilizing the cross-bar circuits to perform conventional specialized operations as well. These operations have a great deal of redundancy in their control state. The present invention describes a system and method for generating the large number of control bits of the cross-bar circuit (e.g. typically more than 1,000 bits) from a much smaller number of control bits for conventional operations (e.g. typically fewer than 100 bits). This invention conserves the resources and delays that would otherwise be incurred in the use of the wide operand memory referred to in the previous paragraph.
The present invention describes a system and method to implement a cross-bar circuit, memory, and control of a switch of a broadband processor, that (1) requires (a) a small area of silicon, (b) very low power, (c) a small number of transistors, (d) a small number of wires, and (e) only two metal layers, (2) operates at a high speed, and (3) has high functionality.
In an exemplary embodiment, the present invention provides a cross-bar circuit that, in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 2
n
-bit (e.g. 256-bit) input source word to be switched into any bit position of a 2
m
-bit (e.g. 128-bit) output destination word and (2) provides the ability to set-to-zero any bit in said 2
m
-bit output destination word. The cross-bar circuit includes: (1) a switch circuit which includes 2
m
2
n
:1 multiplexor circuits, where each of the 2
n
:1 multiplexor circuits (a) has a unique n-bit (e.g. 8-bit) index input, one disable input, and a 2
n
-bit wide source input, (b) receives (i) an n-bit index at the n-bit index input, (ii) a disable bit at the disable input, and (iii) the 2
n
-bit input source word at the 2
n
-bit wide source input, and (c) decodes the n-bit index either (i) to select and output as an output destination bit one bit from the 2
n
-bit input source word if the disable bit has a logic low value or (ii) outputs a logic low as the output destination bit if the disable bit has a logic high value; (2) a cache memory that (a) has 2
m
cache datapath inputs and 2
m
cache index inputs, (b) receives (i) the datapath information on the 2
m
cache datapath inputs and (ii) 2
m
n-bit indexes on the 2
m
cache index inputs, (c) provides a first set of the n-bit indexes for the switch circuit, and (d) includes a small tightly coupled memory array that stores p (e.g. eight) entries of 2
m
n-bit indexes for the switch circuit, where the cache memory is logically coupled to the switch circuit; and (3) a control circuit that (a) has a plurality (e.g. 100) of control inputs, (b) receives the partially-decoded instruction information on the plurality of control inputs, (c) provides a second set of the n-bit indexes for the switch circuit, and (d) provides the disable bits for the switch circuit, where the control circuit is logically coupled to the switch circuit and to the cache memory.
In an exemplary embodiment, the present invention provides a switch circuit that allows any bit from a 2
n
-bit (e.g. 256-bit) input source word to be switched into any bit position of a 2
m
-bit (e.g. 128-bit) output destination word and that provides the ability to set-to-zero any bit in the 2
m
-bit output destination word. The switch circuit includes 2
m
2
n
:1 multiplexor circuits, where each of the 2
n
:1 multiplexor circuits (a) has a unique n-bit (e.g. 8-bit) index input and one disable input, (b) decodes an n-bit index received at the n-bit index input to select one bit from the 2
n
-bit input source word if a disable bit received at the disable input has a logic low value, and (c) outputs a logic low if the disable bit has a logic high value. Also, each of the 2
n
:1 multiplexor circuits includes: (1) a 2
q
:1 pass gate selector (e.g. 4:1 pass gate selector), where the 2
q
:1 pass gate selector has 2
q
precharge/discharge wire-OR bitline inputs; (2) a sense amplifier logically coupled to the 2
q
:1 pass gate selector, where the sense amplifier (a) receives the output of the 2
q
:1 pass gate selector and (b) receives a dummy bitline input to allow differential sensing of small swing signals on the wire-OR bitline inputs; and (3) 2
n-q
unit switch cells (e.g. 64 unit switch cells) per precharge/discharge wire-OR bitline input, where each of the unit switch cells (a) is logically coupled to a wire-OR bitline input of the 2
q
:1 pass gate selector, (b) is logically coupled to one of 2
r
(e.g. one of 8) active-LOW “SELA” select wires, and (c) is logically coupled to one of 2
n-q-r
(e.g. one of 8) active-HIGH “SELC” select wires.
In addition, an exemplary implementation of the present invention provides a control circuit that provides indexes and disable bits. The control circuit includes: (1) an arithmetic logic unit (ALU), where the ALU includes a plurality of ALU modules; (2) a plurality of |multiplexors logically coupled to the ALU, where each of the multiplexors includes a plurality of multiplexor modules; and (3) a plurality of decoders logically coupled to the ALU and to the plurality of multiplexors, where each of the decoders includes a s-stage (e.g. 5 stage) chain of NAND/NOR gates.
Some of the advantage of the cross-bar circuit are as follows:
1. It re
Bateman Bruce
Hansen Craig
Moussouris John
Eakin James E.
Guzman Leonard T.
McDermott & Will & Emery
Microunity Systems Engineering, Inc.
Monestime Mackly
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