Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific current responsive fault sensor
Reexamination Certificate
1999-10-01
2001-10-23
Huynh, Kim (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific current responsive fault sensor
C361S093100, C361S093800
Reexamination Certificate
active
06307726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to improvements to the precision in limiting the output current of a semiconductor device over a broad temperature range through the use of a compensated current limiting circuit.
2. Brief Description of the Known art
It is necessary for semiconductor devices such as integrated circuits to operate over a broad temperature range. A typical temperature range for military applications is −40 degrees centigrade (deg. C.) to +125 deg. C., while many industrial applications require that the integrated circuit (IC) operate within specifications from −40 to +100 deg. C. Special applications, such as automotive, require that the IC operate over a temperature range of −40 to +125 deg. C.
A current limiting circuit is designed to sink (or source) a specified maximum output current from (or to) a load. It is necessary that this current remains below a certain specified design level so that no damage to either the circuit, chip, bond wire or device package occurs. Also excessive current can damage the load being driven. This is particularly important for devices where the output current in normal operation is relatively high, i.e., in the ampere range and above. Excessive current can occur in a device when something abnormal happens to the load, such as a stalled motor or a short to supply. As an example, micro controllers are used to control DC motors such as stepper motors. If the controller fails, excessive current can occur and could damage the motor windings.
A packaging design approach to manufacturing higher current IC's is to use multiple wires on the lead frame and multiple pads on the chip to a single contact. A 1 mil bond wire will reliably carry one ampere DC, but typically fuses at 1.2-1.8 amperes. Therefore, an IC that carries three amperes under normal operation may use three, 1 mil wires between the lead frame and bond pads. A larger 1.3 mil wire will carry two amperes, but will fuse in the 2.5-3.5 ampere range. The IC output current must be limited to a current below the level that will destroy or damage the bond wires, the chip or the load, either in normal or abnormal operations over the required temperature range.
The circuit in
FIG. 1
shows the conventional method used to solve the problem of excess current in the load circuit of the device. This conventional low precision current limiting circuit is simple and economical. It is also very stable because of the low loop gain. It has the desired fast (less than 300 nsec.) response to limiting output current when excessive current is sensed in the output MOSFET. The problem with the conventional circuit is that, over a broad temperature range, the current limiting capability has a wide variation. As an example, in the embodiment discussed later, the variation of output current limiting is 130% going from approximately 600 ma. at +150 deg. C. to 1400 ma. at −50 deg. C. The negative slope at high temperatures is useful as will be discussed later. The desired temperature characteristic, however, would be a flat or relatively flat current limiting characteristic over a broad range and changing to a negative slope at a specific high temperature and beyond.
The operation of the conventional current limiting circuit of
FIG. 1
is as follows. M1 is the output MOSFET transistor in which the current is being controlled. The MOSFET is but one type of a broader class of insulated gate field effect transistors (IGFETs). The balance of the circuit, shown within the dotted lines is the conventional current limiting circuit. M2 is a sensefet and may be any area ratio with respect to M1. In a typical case, it is approximately {fraction (1/100)} the area of M1, but made in the same MOS process as M1, with the same temperature characteristics except scaled for size. The area of the sensefet can be varied depending on the current amplification desired. The ratio of the current in the two transistors varies in proportion to the ratio of the areas of the two devices.
Current
in
M1
Current
in
M
2
=
Area
of
M1
Area
of
M2
As the current in M1, at node N1, reaches the maximum design current, the voltage at node N2 reaches the base-to-emitter “on” voltage (V
beon
) of the transistor T1, and the transistor turns on. This reduces the voltage at node N3 to V
ceon
, lowering the gate voltage of the output MOSFET at node N3, thereby maintaining the current through M1 below the design maximum. In a typical embodiment, R1 might be 70 ohms. The current limiting level of the current limiting characteristic can be modified by the value of this resistor. Increasing R1 will lower the current limiting capability (increase the current limit) and lowering the resistor will have the opposite effect. R2 is a polysilicon 10 K ohm resistor. The size is determined by the normal operational response required and minimization of the RF or EMI generated by the circuit pulses. In a typical embodiment, an acceptable operation response time is 300-700 nsec. The V drive is a reference voltage and is generally in the 0-15 volt range.
The low precision current limiting circuit has proven very effective when the operating temperature range is limited. The serious drawback of the circuit is that it is highly dependent on temperature and exhibits unacceptable variation in its current limiting capability over a broad temperature range as shown in Table 1. The V
beon
of transistor, T1, typically has a negative temperature coefficient of 1.8 mv./deg. C., and the resistor, R1, has a positive temperature coefficient of approximately 1000 ppm/deg. C. Depending on the process, both the transistor and resistor coefficients will vary, but the values given above are representative. As the operating temperature increases, the V
beon
of the transistor, T1, is reduced and the transistor turns on at a lower voltage, hence lowering the voltage at node N3. The maximum current limited output at M1 is lowered. As the temperature is reduced, the opposite effect occurs and the maximum current limited output at M1 increases.
TABLE 1
V
beon
(T1)
Temperature
@ N2
Resistor, R1
Current @ M2
Current @ M1
(deg. C)
(volts)
(ohms)
(ma)
(amperes)
175
0.42
80
5.3
0.53
100
0.56
75
7.5
0.75
25
0.70
70
10.0
1.00
−50
0.84
65
12.9
1.29
In Table 1:
Column 1 gives the ambient temperature of the circuit.
Column 2 is the Vbeon of transistor T1. The values given are for a negative temperature coefficient of 1.8 mv./deg. C.
Column 3 is the temperature dependent resistance of resistor, R1, with a positive temperature coefficient of approximately 1000 ppm/deg. C.
Column 4 is the current through the sensefet, M2, and is calculated as:
I
M2
=V
beon
/R1.
Column 5 is the through the drive MOSFET, M1, and is calculated as:
I
M1
=I
M2
×100 (current mirror amplification)
As can be seen from Table 1, the variation in current limited value, when only using the conventional circuit, is large over a broad temperature range varying from 0.53 amperes at +175 deg. C. to 1.29 ampers at −50 deg. C. This calculated data compares favorably with the chart that shows actual measured data in FIG.
5
. These large variations are very difficult and expensive for circuit designers to overcome.
SUMMARY OF THE INVENTION
The invention uses the best characteristics of the low precision current limiting circuit of
FIG. 1
in combination with a new compensation circuit to achieve essentially a flat or controlled current limited output response from the output MOSFET over a wide variation of operating temperature. The compensation circuit develops a current that varies with temperature in a specific manner. This current, which is injected into resistor, R1, serves to compensate for temperature induced variations in the V
beon
of transistor, T1, and the resistance of resistor, R1. The result is that, o
Lin Ching L.
Marshall Andrew
Xu Jingwei
Brady III Wade James
Huynh Kim
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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