Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1999-06-11
2003-11-18
Marcelo, Melvin (Department: 2663)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C326S032000, C327S262000, C327S407000, C341S119000
Reexamination Certificate
active
06650661
ABSTRACT:
BACKGROUND OF THE INVENTION
2. Prior Art
The proliferation of computers and related electrical machines, such as routers, switches, servers, etc., have created a need for improved interconnection devices and methods. The need is present not only at the box level, but also at the sub-assembly level. The box level relates to interconnecting standalone boxes, such as workstations, personal computers, servers, routers, etc., whereas the sub-assembly level relates to components such as ASICS, modules, etc., within the boxes.
Traditionally two interconnecting approaches or techniques have been used. In one technique, a bus structure does the interconnection. Even though bus structure transfers data relatively fast, it is expensive and requires multiple pins (one for each bit) at the interface. There are many designs in which pin counts and cost are very sensitive issues. As a consequence, bus structures are not suitable for interconnecting sub-assemblies.
In the other approach, a serial link is used as the interconnecting mechanism. Even though the serial links solve some of the problems associated with the bus structures, they too have shortcomings which limit their use. Probably, the most severe of all the shortcomings is that the serial links are relatively low speed. For example, an RS232 serial link transmits data at approximately 115K bits/sec. Surely, this speed makes them unsuitable for use in high speed, say 500 and greater Mbps, applications.
The prior art has provided serial link devices with speed greater than RS232, albeit less than 500 Mbps. Even though these systems point in the right direction, they suffer several defects including unnecessary use of pins to transmit clock signal, etc.
Examples of the prior art systems are set forth in the following US patents:
U.S. Pat. No. 5,081,654
U.S. Pat. No. 5,651,033
U.S. Pat. No. 5,533,072
U.S. Pat. No. 5,587,709
U.S. Pat. No. 5,675,584
U.S. Pat. No. 5,714,904
In view of the above, there is a need for a more efficient high speed interconnection system.
SUMMARY OF THE INVENTION
The interconnection system of the present invention is termed Data Aligned Serial Link (DASL) Interface. The DASL Interface receives data from a parallel interface such as a CMOS ASIC, partitions the bits from the parallel interface into a smaller number of parallel bit streams. The smaller number of parallel bit streams are then converted into a high speed serial stream, which is transported via a transmission medium to the receiver of the other module. A differential driver with control impedance drives the serial bit stream of data into the transmission media.
By simultaneously transmitting groups of bit streams serially over different transmission media, a high speed, high volume data path is provided. The data path uses fewer pins and transfers data at a faster rate than a traditional bus structure.
Prior to sending actual data, the system is initialized with a training procedure that sends a training pattern from the transmitter on one module to the receiver on the remote module. Preferably, the training pattern includes a 32-bit transmission rich sequence of 7 hex “A” patterns (1010) and 1 hex “5” pattern (0101). The purpose of the training pattern is to provide sufficient pattern edges so the receiver, through its algorithm, can acquire bit synchronization and then nibble synchronization to establish the most and least significant bits in the serial data stream when the bit stream is converted back into a 4-bit nibble.
The received data from each transmission medium is processed separately. The receiver converts the data into a single ended signal which is delayed over-sampled and latched. A controller examines the captured over-sampled data to determine wherein the series of latched positions data transition occur.
This is done to determine two sample points in the stream of over-sampled data with the highest probability of uncorrupted data. The oversampled data which has the least probability of data error is the oversampled data contained in the latches farthest away from the data transitions. This is because all high speed systems have data jitter in the form of the system clock jitter, data intersymbol and transmission media distortions as well as system crosstalk that make the sample around data transitions uncertain as to data integrity. By averaging of the positions determined to have transitioning data, the controller then determines which of the latched data to be used for the serial data samples. The sample points are selected by taking the locations of the data latches where data transitions occur, subtract the location numbers and add half the difference to the smaller location (done for two sequential data bits, giving two strobe positions). The controller acts as a digital software filter though this process by accumulating and averaging transition information and supplying the result of the accumulated data. This is important in that the best sample point is the point based upon the average points of transition, so as the sample does not respond to one piece of jitter, readjust its sample point and then sample the next bit in a location where the data integrity is uncertain. When actual data is sent in place of the training pattern, the sampled data will contain long run lengths where no transitions are present. When this occurs, no update in the algorithm sample point will occur.
The controller continuously executes an algorithm that detects changes in the position of the sample points in the delay line. When appropriate, new settings are calculated for the MUX
28
and MUX
30
(FIG.
5
). To evaluate the current settings of MUX
28
and MUX
30
, the controller requests and processes an Edge Detect Sample to detect if the data has shifted in the delay line relative to the current multiplexer settings. An Edge Sample is a snapshot of the data in the delay line. The processing provides new calculated values that are filtered to ensure that the update does not track the normal jitter in the system.
The continuous updating by the controller algorithm also adjusts out temperature and initial technology process effects by basing the strobe point on the received data pattern strictly on the ongoing results of processed data input logic edges. As the transition edges move with temperature, so do the sample points. The controller can be time shared in applications having multiple high speed serial links, using only one controller functions for all links, to reduce cost.
The delay line also assist in compensating for process variation.
Once the data stream has been adjusted for the best sample points, the two selected data streams are then fed into a series of latches and passed through two multiplexers (
FIG. 8
, MUX
46
, MUX
52
). Access of the output nibble is provided to the controller for adjusting the bits into their proper parallel order. The output nibble bit order is adjusted by the controller through manipulations of the control inputs to MUX
46
and MUX
52
.
To reconstruct the 4 bit nibble into its correct parallel order, an initial training pattern is supplied to the receiver, supplying a repeating pattern into the receiver with a unique end bit (7 “A's”, followed by a “5”). Adjustment of the bit order is performed by the controller which compares the serial string against a lookup template and through its various software states, adjust the nibble bit position.
REFERENCES:
patent: 5081654 (1992-01-01), Stephenson, Jr. et al.
patent: 5533072 (1996-07-01), Georgiou et al.
patent: 5587709 (1996-12-01), Jeong
patent: 5651033 (1997-07-01), Gregg et al.
patent: 5675584 (1997-10-01), Jeong
patent: 5714904 (1998-02-01), Jeong
patent: 6185693 (2001-02-01), Garmire et al.
patent: 6348826 (2002-02-01), Mooney et al.
patent: 6441659 (2002-08-01), Demone
patent: 2002/0172311 (2002-11-01), Chen et al.
IBM Technical Disclosure Bulletin “Flexible Assembler/Dissembler of an Aggregated Communication Link” vol. 34, No. 12, May 1992.
IBM Technical Disclosure Bulletin “Adaptive Use of Parallel Serial Links” vol. 39, No. 06, Jun. 1996.
Buchanan Brian
Gray Carl Thomas
Riedle Christopher G.
Rizzo Raymond Paul
Cockburn Joscelyn G.
Marcelo Melvin
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