System providing multiple fetch bus cycle operation

Details System providing multiple fetch bus cycle operation System providing multiple fetch bus cycle operation

1978-01-05

1980-11-25

Thomas, James D.

Boots, shoes, and leggings

G06F 104, G06F 1300

Patent

active

042362032

ABSTRACT:
In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.

REFERENCES:
patent: 3710324 (1973-01-01), Cohen
patent: 3997896 (1976-12-01), Cassarino, Jr.

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